Withnails writeup is correct, but one very important problem of CMOS is not mentioned:
PMOS transistors turn on if there is a positive voltage difference between source and gate at a certain level and NMOS turn on if the difference is negative. This implies that PMOS transitors are only good swichtes when using VDD as source and NMOS are only good switches for VSS - if e.g. PMOS is used with VSS it uses the other pin as reference. However, this voltage on this pin is pulled down and when it has reached a certain level > 0, the transistor turns off. So the output is not pulled down at VSS but a slightly higher level. If you put several such transistors in a row (connecting the output to the gate of the next transistor) you would get totally screwed up voltage levels.

Therefore PMOS are usually used as switches to VDD and NMOS to VSS. This gives most basic gates an "inverting" character: You can only get a logical 1 output with logical 0s at the gates of the PMOS transistors and a logical 0 is produced by logical 1s at NMOS transistors. It is not possible to build an AND or an OR by just on stage of transistors, you must always put some in a row or use inverters.

Another effect is that some standard logic gates become very asymmetric. Let's take an NOR as an example:

                    ___ VDD
       +------------|   PMOS transistor
       |             |
       |       +----|   PMOS transistor
 in B -+       |     |
       |       |     +------------------- out
       | in A -+     |
       |       |  +--+---+
       |       |  |      |
       |       +-|    +-|   2 NMOS transistors
       |          |   |  |
       |         ---  | ---
       |         VSS  | VSS
This would be a standard implementation of a NOR2, it computes out = not(A or B). The path from VDD to out has 2 transistors in series, the path from VSS to out 2 transistors in parallel. As you might expect, switching out from logic 1 to 0 would be faster than switching from 0 to 1. (same speed PMOS and NMOS transistors assumed). For a NOR2 this would be not problematic, but imagine larger gates like a NOR100 !. The are several tricks to get around this, e.g. dynamic logic.

Electrical engineers would point out that the upper explanation is not 100 percent correct, but I find this one easiest to understand. The effect of bad switch against VDD/VSS can also be explained by lots of calculation with equations describing the behavoir of a transistor.