Standard CMOS logic has sometimes the problem that it has an highly asymmetric structure of the transistor networks. Another problem is that for large logic functions the fan-in of the function when build in CMOS gets too large.
A way to avoid this is using dynamic logic. Contrary to the standard logic gates, which are also referred to as static logic, dymanic logic doesn't calculate the outcome of a changing input at once. It is clocked and uses several clock ticks (in fact 2) to calculate the value of the function.
The idea behind it is quite simple: You put a capacity (a capacitor or the gate of a CMOS transistor) at the output of the function. In the first clock cycle the capacity is carged with a VDD voltage. At the second cycle the capacity is decharged iff the function evalutes to 0.
What's the benefit of this sheme ?
You can spare nearly an entire network of PMOS transistors, thereby reducing fan-in and increase switching speed.
Lets have a look at a picture to make this clearer:
```                ___ VDD
|
NPRECHARGE---|   PMOS
|
+--------------+------------ output
|              |
+-----------+       --- capacitor
| standard  |       ---
function | NMOS      |        |
inputs --| switching |       ---
| network   |       VSS
| for the   |
| function  |
+-----------+
|
NPRECHARGE --|   NMOS
|
---
VSS
```
The detailed working of the circuit:
1. NPRECHARGE is low (logical 0). The PMOS transistor turns on, the NMOS off. The capacitor is charged by the current path to VDD. The output is at logical 1.
2. NPRECHARGE is high (logical 1). The PMOS transistor turns off, the NMOS on. The capacitor is decharged iff the NMOS switching network of the function opens a current path to VSS. Therefore the capacitor (and the output) falls to VSS iff the function has the output 0.
So you trade the entire PMOS network of the function and with it half of the fan-in for the additional transitors and 2 clock cycles switching time. However, for large functions the fan-in and lots of transistors in series of the function as a standard CMOS cell would cause the same switching time as 2 clock cycles (or even longer).
The upper example is for deleting the PMOS network, but you can do this of course with the NMOS network, too. Just use NOT(PRECHARGE) for "charging" the transistor to 0.

Dynamic logic can cause some problems when used in a row, but you can get around these by using domino logic (just putting an inverter at the output) or different clocking schemes.

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