Circuitry that is highly miniturized and tightly packed. IC's are photolithographically deposited onto the surface of semiconductors like Silicon and Gallium Arsenide. Individual circuit elements (usually transistors) are often less than one micron^2 in size and are connected by metals like Aluminum and Copper. Companies that have mastered the art of wafer fabrication include IBM, Intel, Motorola and Texas Instruments.

The development of the integrated circuit (IC) is one of mankind's most impressive and most life-changing achievements.

This writeup is a nontechnical introduction to the fabrication of integrated circuits. Other nodes such as CMOS, MOSFET, and digital circuit design provide complementary information about how integrated circuits perform their various tasks.

An integrated circuit is an electronic circuit, such as a microprocessor, that is self-contained on a chip. A finished integrated circuit can consist of millions of tiny semiconductor devices connected by billions of metal interconnects. While one can buy individual semiconductor devices (at Radio Shack for instance) and one can wire devices by hand, manually wiring a circuit of such great complexity is clearly impractical. Even if it were possible to form such complex non-integrated circuits, they would have the following problems: extremely slow performance and high power consumption due to parasitic wiring resistance and capacitance, poor reliability, huge size, and unfeasible cost. An interesting writeup on how a non-integrated digital computer was constructed in the 1940s using vacuum tube transistors is given under ENIAC.

Before we discuss how an integrated circuit is fabricated, it is useful to have a picture of a finished chip in mind. The finished chip will have dimensions of around 2cm length x 2cm width and 0.5mm thickness. The 2cm x 2cm area will be covered with many (perhaps millions) of transistors, which are the critical devices in a circuit. The transistors are composed of a variety of materials stacked on top of eachother (see MOSFET for a greatly simplified diagram). The transistors are connected to other transistors by several layers of metal. The fabricated chip looks like a large metropolis with the metal interconnect wires forming a futuristic stacked highway system.

There is an excellent website with diagrams of the fabrication of a p-n junction and an n-MOSFET. It would be extremely useful to refer to those diagrams when trying to visualize the processes below. The p-n junction site also includes photos of the wafer and the fabrication equipment. The addresses are below.

OK, enough background! Let's talk about how an integrated circuit is made. Please note that I can only provide the bare essentials of IC fabrication here. Perhaps other nodes will provide more in-depth information about each process step.

First of all, we have to do every step in a cleanroom and we need to dress in some clothing (a bunny suit) that doesn't produce particulates. Cleanrooms have filters that greatly reduce the number of particles in the air. Stray particles that land on our wafer could destroy our entire circuit!

We start with a circular wafer with perhaps an 8-inch diameter and a 0.5mm thickness. The idea is to produce many chips simultaneously from this wafer so that they are cheap. At the very end we'll dice the wafer into chips and package them. We would like to have as big a wafer as possible, though we need to maintain quality across the entire wafer. The wafer might seem really thin. It turns out that we'll only use the uppermost 1% for devices. The reason the wafer is so thick is to prevent cracking. For most purposes, the starting wafer is crystalline silicon. For information on how this wafer is produced, see Czochralski method.

The three most fundamental processes in microelectronic fabrication are the following:

Deposition of materials

To make our transistors, to electrically isolate them from eachother, and to interconnect them, we're going to need layers of metal, insulators, etc. Actually, we need more than that--we need patterned layers. Unfortunately, there is no good way to deposit layers of materials exclusively where we want them on the wafer with reasonable accuracy. Since our chip is about 2cm x 2cm and we want millions of individual transistors on that chip, it is clear that we need very precise (submicron) patterning of layers. Our plan will be to deposit materials across the whole wafer and later etch them away from undesired locations.

There are many ways to deposit different materials onto and into the wafer. The most important are the following:

Evaporation is a method to deposit metallic films like aluminum and gold. The simplest way to evaporate metals onto the wafer is to hang them from filaments above the wafer and heat the filaments. When the metals get hot enough, they evaporate onto the wafer. A more advanced evaporation method, called E-beam evaporation, uses a high-intensity beam of electrons to strike a metallic target above the wafer. The electrons, with energies up to 15keV, melt a portion of the target and the material covers the silicon wafer.

Sputtering is fairly similar to evaporation, but generally superior. During sputtering, a material above the wafer is bombarded with very energetic ions--usually Ar+. Atoms near the surface of the material are blasted free and deposited onto the wafer. Sputtering is used to deposit materials ranging from metals to insulators. It is also a very good way to deposit alloys.

Chemical Vapor Deposition (CVD) is the most flexible way to deposit materials. Wafers are put in a furnace connected to various gas inlets. Reactive gases are introduced into the furnace. The gases diffuse to the wafer, where they decompose and react, leaving the desired material on the wafer. As an example, polysilicon, the gate material of most MOSFETs, is deposited in an LPCVD (low pressure CVD) system at 600 °C by the following reaction: SiH4------->Si + 2H2(g). The extraneous gaseous products are removed through furnace outlets. CVD is usually used to deposit insulating materials and polysilicon, though it can be used to deposit many metals also.

It is important to note that the high temperatures involved in CVD affect everything on the wafer. If there were aluminum on the wafer during the polysilicon deposition above, it would melt! High temperatures can cause dopants to diffuse throughout the wafer. Sometimes this is desired but often it is not. One way to reduce the temperature of the CVD process is to use plasma-enhanced CVD (PECVD). During PECVD, high-energy ions generated in a plasma are used to help stimulate chemical reactions on the wafer, allowing a reduction of temperature.

Thermal growth is almost identical to CVD but is usually not referred to as CVD. The only difference between thermal growth and CVD is that thermal growth involves gases reacting with the silicon wafer instead of just adding to it. The most important example of thermal growth is the growth of the gate oxide in a MOSFET. Here O2 gas is introduced into the furnace at a temperature ranging from 900 to 1200 °C. It reacts with the silicon surface to form very high-quality (though still amorphous) SiO2.

Ion implantation is used to implant dopant atoms into the silicon. Typically the word deposition isn't used in reference to ion implantation, but ion implantation is similar to deposition in that it involves substances being added to the wafer. The dopants make the silicon p-type or n-type depending on whether the dopants are acceptors or donors. Common donors are phosphorus and arsenic while boron is the only common acceptor. During ion implantation, gases such as arsine, phosphine, and diborane are ionized by a plasma generator. An electric field is used to accelerate the ionized dopants toward the wafer. The dopants can be excited to energies up to about 175keV. The type of dopant and the implantation energy determine how far the dopants are driven into the wafer. After implantation, a high-temperature anneal step is necessary to activate the dopants and to repair damage to the silicon crystal.

There's one more thing I should note about ion implantation. Implantation is done after lithographic patterning. Either photoresist or another material on the wafer acts as an implantation mask.


After we deposit a material all over the wafer, we need a way to pattern it. Patterning is accomplished by a process called lithography. Lithography is the most difficult and demanding fabrication step. What we want to do is cover the wafer with some special substance, change the chemical properties of that substance in certain locations, and then selectively remove the material from those locations (alternatively we could remove material from everywhere except those locations).

In modern IC fabrication, the special substance is called photoresist. Photoresist is an organic liquid that is spun onto a wafer at 1000 to 5000 rpm and hardened. It coats the wafer with a film of about 1 micron thickness. Upon exposure to light of a resist-dependent wavelength, photoresist becomes significantly easier to wash away in a liquid called developer. What we do is shine light of that wavelength through a glass mask patterned with some opaque regions and some transparent regions. This is called exposure and is done in a machine called a mask aligner or stepper. The patterned features on the mask don't have to be as small as the features we want on the wafer because we can focus the light with lenses. Now we dip the wafer in developer until the photoresist is completely washed away from undesired locations.

The smallest features that can be patterned are on the order of the wavelength of the light used during exposure. Smaller features are desirable for two main reasons. MOSFETs, the most important silicon devices, switch faster when they are smaller. This means we can use a higher clock rate. Furthermore, if devices are smaller then we can put more on a chip of the same area. Over the years, the minimum feature size has gotten smaller and smaller, and accordingly microprocessor speed has increased and the density of memory chips has grown.

To maximize resolution, ultraviolet (UV) light sources with wavelengths of 100-400nm are used. If we want even smaller features, we'll have to use new sources and new resists sensitive to those sources. Unfortunately, this is easier said than done. Much industrial and university research has been invested in extreme ultraviolet (EUV) lithography. A practical EUV light source would have a wavelength of around 50nm. The EUV process is challenging since there are no lenses for EUV light. One proposed solution is to use mirrors to focus the light.

If we want to pattern extremely small features on the order of tens of nanometers, we can use electron beam lithography. In e-beam lithography, the "light source" is actually a focused beam of electrons and an electron-sensitive resist like polymethyl methacrylate (PMMA) is used. The problem with e-beam lithography is that it takes a very long time to expose the resist since the focused beam has to be "written" across the entire wafer. Better resolution requires slower writing times. The throughput of e-beam lithography is so low that its cost has prohibited its use in commercial integrated circuits. However, it is a useful, widely-used research tool.

At this point we have patterned photoresist, but that's not what we want. We want some other material--polysilicon or silicon nitride or aluminum or silicon dioxide or etc.--patterned. So we're ready for the final step...


Let's review the state of our wafer. It has an unpatterned layer of some material that we want to pattern. On top of this material is a layer of photoresist with openings where we want to remove our material. Now it's time to etch!

There is one critical thing to keep in mind when etching. We want to remove only the material intended to be etched. If we're etching aluminum, we don't want to etch aluminum and everything underneath it. Furthermore, we should make sure we don't etch the photoresist as quickly as we etch the aluminum because then we lose our ability to pattern. In other words, we want our etch to be selective. Tables exist that list the etch rates of a particular wet or dry etch for several materials. Fortunately, accidental photoresist removal is rarely an issue.

Of course, we could try to time our etch so that we stop etching exactly when we've removed our target material and before we can damage the underlying layer. Then our etch wouldn't need to be selective. The problem with this approach is that in reality, the thickness of our target material varies greatly across the wafer depending on the topography beneath it. Attempting to precisely time our etches isn't a hot idea.

The two basic types of etches are wet etches and dry etches.

For a wet etch, the wafer is dipped in...surprise...a liquid solution. This solution is almost always acidic. A common wet etchant is hydrofluoric acid (HF). HF is used to etch silicon dioxide without etching underlying silicon at all. Thus it is perfectly selective to silicon. Consider the fact that HF will etch any SiO2 with which it comes into contact. After the HF etches a little bit of SiO2, it comes in contact with SiO2 that used to be under masking photoresist. Therefore the holes in our oxide will be bigger than the holes in our photoresist. Sometimes this undercutting is a good thing. Often it is a bad thing. Microfabrication isn't trivial.

Dry etching uses energetic ions that bombard the wafer, sputtering off material. Nonreactive ions like Ar+ can be used, but these aren't selective at all. It is better to combine the physical sputtering mechanism with chemical reactions by using reactive ion etching (RIE). We first pump gases containing the chemical species we want into an evacuated chamber. Using an RF generator, we form a plasma from the gases (basically we ionize the gases). Then we use an electric field to drive the ions toward the wafer. Dry etching does not have the undercutting problem of wet etching. On the other hand, wet etching is cheaper and has higher selectivities.

Putting it all together

Well now we have one layer patterned and we can start another one. We always have to consider whether additional processing will affect what we've already done.

Producing a complex circuit like a microprocessor takes tons of planning and coordination. Fabrication engineers design the sequence of process steps that will be used for the integrated circuit. They give circuit designers a set of design rules for the process that dictate how small features can be, how far apart features have to be spaced, etc. Fabrication engineers also give the circuit designers information on things like the measured sheet resistance of layers. They provide hundreds of measured parameters that govern the performance of the all-important MOSFETs.

The circuit designers use this information to layout a circuit using computer aided design (CAD) tools. The layout is used to generate lithography masks. Using the circuit simulator SPICE and the measured parameters given to them by the fabrication engineers, the circuit designers can make sure their circuit will operate properly before investing time and money in IC processing.

I hope you found this useful. Please /msg me if you find mistakes or if you would like additions.

This writeup is a collection of links to additional information about integrated circuits (IC's). In some cases I have located the nodes. In other cases the nodes should exist but do not. This is not a complete list of every writeup related to integrated circuits. Instead it is a list of nodes of generality a tier or two below this one. Hopefully this list will point readers to the more specific information they desire.


Circuit design

Fundamental IC devices

  • See semiconductor
  • Processes and techniques


    IC companies

    Miscellaneous links

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