A *half adder* is an important part of of what may be called a *full adder*. The full adder has the ability to add *any* two binary digits together, whether the output has a carry or not.

The *half adder* can only add two binary digits together and output one digit. The carry is not taken into account.

** Full adder** ** Half Adder**
1 1
__+ 1__ __+ 1__
10 0

With the half adder we only get a one digit output.

**Well how do we make one of these 'half adders'?**

We use things called logic gates.

*Note*: Before you continue reading, please ensure you have read the logic gates node, I say this so you will have a basic understanding of what is to follow.

First of all we'll need to draw up a

truth table of our desired outputs. We will use this truth table to test our logic gate diagram. Having two inputs you will have only 4 possible binary combinations.

I_{1} I_{2} **O**
____________
0 0 | 0
0 1 | 1
1 0 | 1
1 1 | 0

Looking at our output column we can see that the pattern of outputs is somewhat similiar to the output of an OR gate. Shown below.

**OR** **O**
_______
0 | 0
1 | 1
1 | 1
1 | 0

The only output that is different is when both inputs are 1. We'll start the diagram with an OR gate, this will take care of the first three inputs. But we also need something to take care of the last output.

*Note*: I'd probably defeat my own purpose if I tried to explain the complete logic gate diagram in words so I'll make a bad attempt at ASCII art.

First we need an

OR gate.

___
I1 -------\ `-._
\ `.______
/ _,'
I2 -------/___,-'

We now take the

output of the OR and feed it into an

AND gate:

___
I1 --------\ `-._ ___
\ `._________| `-.
/ _,' | \_______
I2 --------/___,-' | /
|___,-'

As we look at the output of the AND gate we can see that if one input is 0 then the output will also be binary. This is a very important discovery!

AND Gate
I_{1} I_{2} **O**
____________
0 0 | 0
0 1 | 0
1 0 | 0
1 1 | 1

Using this

important information, we now know that we can use the AND gate as a switch of sorts.

*How?* Well, consider this: If we were to make one input of an AND gate a 1, then the output would be the same as the second input. Take this for example:

AND Gate
I_{1} I_{2} **O**
____________
1 0 | 0
1 1 | 1

So, when we **know** the first input of an AND gate will be 1, then we **know** that the output of that AND gate will be the same as the second input.

In saying that, when I_{1} is 1 then the switch is open and I_{2} will go through as the output. *This* is why we have an AND gate after the OR. The OR will give us an output of 1 if it has an input of 1. So the AND gate/switch will be open whenever there is a 1 as an input.

And having established **that**, we can now carry on with the logic gate diagram.

So far we have:

___
I1 --------\ `-._ ___
\ `._________| `-.
/ _,' | \_______
I2 --------/___,-' | /
|___,-'

We now need to have a look at our AND gate's second input. We know that the first two inputs of 0 and 0 will give us a 0 as the AND gates first input. This means that the output will, of course, be a 0.
So all we need to look at is the next three inputs. We want them to be as follows.

When... We want...
I_{1} I_{2}
_________________
0 1 | 1
1 0 | 1
1 1 | 0

Looking at these three outputs we look and see if there is a

pattern...

and is there?
We already know that a normal AND gate's output is:

AND Gate
I_{1} I_{2} **O**
____________
0 0 | 0
0 1 | 0
1 0 | 0
1 1 | 1

We're only interested in the last three outputs though.

Lets compare them with our desired outputs.

**Desired AND Gate's**

Output Output
_____________
1 | 0
1 | 0
0 | 1

Well, there you go! They're opposite as we can quite plainly see. So the second output of our AND gate is the output of another AND gate. Only this AND gate's output will be reversed.

*Well, how do I reverse an output?*

To reverse an output you need a NOT gate. Basically a NOT gate is just a negating gate. It has one input and one output. The output is opposite to the input.

The final diagram:

___
I1 --+-----\ `-._ ___
| \ `._________| `-.
| / _,' | \_______ Output
I2 --|--+--/___,-' | /
| | +-----|___,-'
| | o
| | |
| | / \
| | ___ /___\
+--|--| `-. |
| | \_____|
| | /
+--|___,-'

The final output of our wonderful diagram is:

I_{1} I_{2} **O**
____________
0 0 | 0
0 1 | 1
1 0 | 1
1 1 | 0

Many thanks to

TenMinJoe who has kindly pointed out to me that this truth table is recognisable as the

XOR truth table. XOR is basically a half adder.

References:

David Hartley - Verdon College, Invercargill, Southland, New Zealand. (My computer teacher)

Many thanks also to dinkypoo's logic gates node - I kinda copied his ASCII Art.