Nobody has noded about how a MOSFET is fabricated. I will outline the standard bare-bones fabrication process. Obviously Intel incorporates several more process steps in the fabrication of transistors for a Pentium chip. All of the fabrication processes used are discussed in the node integrated circuit.
I will assume that wells and isolation have already been formed. After isolation, the wafer looks (in essence, not actuality) like this (see LOCOS):
_______ ___________ _________
| | | |
| | | |
Field |___________| Field |___________| Field
oxide | | oxide | | oxide
| Active | | Active |
_______| area |___________| area |_________
Channel Channel Channel
stop stop stop
Doped silicon wafer (or well)
The MOSFETs will be created in the active areas and they will be isolated by the field oxide and channel-stop implantations.
The first step is to grow an ultrathin (the thinner the better down to about 1-2nm) gate-oxide layer on the silicon wafer. Next, a polysilicon gate (and interconnect) layer is deposited by chemical vapor deposition (CVD). The wafer now looks somewhat like this:
------- ----------- --------
Poly | |Polysilicon| | Poly
| | | |
_______ ----------- ___________ ----------- ________
|Polysilicon| |Polysilicon|
| | | |
Field |===========| Field |===========| Field
oxide | | oxide | | oxide
| Active | | Active |
_______| area |___________| area |_________
Channel Channel Channel
stop stop stop
Doped silicon wafer (or well)
======= is the thin gate oxide
At this point lithography is used to define the gate. After photoresist is spun on the wafer and patterned, the polysilicon is etched by reactive ion etching (RIE). There is no reason to etch the thin oxide at this point. Now, the sources and drains of the MOSFETs are formed by ion implantation. The field oxide and polysilicon gate act as natural implantation masks. This is great! The gate, the sources and drains, and the isolation are all perfectly aligned by this process! The implanted ions easily go through the thin oxide above the source and drain regions.
The sources and drains are doped of opposite polarity to that of the wafer (or well). For example, if the wafer is p-type, the source and drain are doped n+, forming an NMOSFET. Since CMOS requires both n+ and p+ source and drains, it requires differently doped wells. The wafer looks like this after source/drain implantation:
_______ --- ___________ -- _________
| |Po | | | |Po | |
| |ly | | | |ly | |
Field |===========| Field |===========| Field
oxide | S | | D | oxide | S | | D | oxide
|___| |___| |___| |___|
_______| |___________| |_________
Channel Channel Channel
stop stop stop
Doped silicon wafer (or well)
======= is the thin gate oxide
S stands for source
D stands for drain
Finally an oxide layer (sometimes called intermediate oxide) is deposited on top by CVD. This oxide is patterned by lithography and etched by RIE so that the sources and drains and the polysilicon gate are exposed. A metal layer such as aluminum is now deposited by sputtering to contact the gates and sources and drains. Actually, we can use the metal to interconnect the MOSFETs too. Voila, we've made a simple integrated circuit. More metal layers could be added if the integrated circuit is complex enough to require multiple interconnect layers, though a single interconnect layer is enough to do a whole lot of things on a chip.