Registers in AMD's Hammer Architecture

A lot of people have wondered, just what is in the Hammer architecture that's going to revolutionize computing? What makes the processor 64 bit? And for those who know something about computers, the eternal question is, are we finally going to get away from the minuscule number of general purpose registers in the x86 architecture?

The answer is found easily in the AMD x86-64 Architecture Programmer's Manual, a five-volume set which AMD will ship you on paper and CD-ROM for free. Of course, you can download it as well.


x86 16 bit     x86 32 bit     x86-64
AX             EAX            RAX
BX             EBX            RBX
CX             ECX            RCX
DX             EDX            EDX
DI             EDI            RDI
SI             ESI            RSI
BP             EBP            RBP
SP             ESP            RSP

On 16 bit x86 intel CPUs (8080 through 80286) you have eight GPRs (general purpose registers) to work with. In practice, only four of them are actually general purpose because the others are used for addressing. Assuming you are doing both source and destination addressing at the same time, this ties up DI and SI. SP is your stack pointer and so it is generally not available for your use, and BP is a secondary stack pointer often used for addressing data. Realistically this leaves us with four 16 bit general purpose registers: AX, BX, CX, and DX. Each of these can be addressed as two eight bit registers; AH and AL (high and low), BH and BL, et cetera.

32 bit intel CPUs have 32 bit general purpose registers; No more of them, but they are all twice as long. You may alter AX without altering the high 16 bits of EAX.

x86-64 defines 64 bit general purpose registers, in addition to defining eight completely new registers, R8 through R15. Unlike the A-D registers, these cannot be broken up into smaller pieces of 32, 16, or 8 bits, and they are only available in x86-64 native mode.

     64                                                             1
BIT  4321098765432109876543210987654321098765432109876543210987654321
REG  RAX --------------------------->EAX------------>AX------------>|
REG8                                                 AH---->|AL---->|

The Hammer CPU has two modes; a "legacy mode" in which it acts like a 32 bit x86 processor, and a "long mode" in which it behaves as a 64 bit processor and applications have access to 64 bit registers. Legacy mode is divided up into real mode, virtual mode, and protected mode, which grant access to various registers and which imply the length of your GPRs. Long mode requires a 64-bit operating system; It will run 32 or 16 bit code in what it calls "compatibility mode". This is essentially equivalent to 32 bit intel CPUs going into real mode to execute 16 bit code; All of the registers look as if they were 16 or 32 bit registers to your program. This is made relatively trivial by the fact that there are generally different opcodes for versions of a processor instruction for different data sizes.

R8..R15 are not the only new registers in the x86-64 set, though they are the only new general purpose registers. Some other new registers are made available in 64 bit mode: XMM8..XMM15, eight new 128 bit "media" registers. The XMM0..XMM7 registers were created by intel for SSE/SSE2 instructions. AMD's Athlon XP processors emulate SSE; Hammer adds SSE2 support. SSE and SSE2 operations generally work on packed data, which is not formatted as a simple binary number. Sometimes they work on vectors, where there are multiple data elements in a single register.


  1. Advanced Micro Devices, Inc., AMD x86-64 Programmer's Manual Volume 1 - Application Programming. AMD, 2002.