The new series of 64-bit microprocessors being produced by AMD embodying their new x86-64 architecture. As opposed to the revolutionary changes towards VLIW and RISC being promoted by Intel's Itanium/Merced architecture, x86-64 is more of an evolutionary change over the venerable IA-32 architecture that has been with us for the past 15 years.

There are two CPUs in AMD's Hammer line that are going to be produced in the very near future (already they have shown demonstration systems at several trade shows like last month's Intel Developer Forum): the Sledgehammer and Clawhammer CPUs. The former is a more powerful system intended for industrial strength server applications and high-end multiprocessor systems, while the latter is a cheaper, less powerful processor planned for mass market use, designed primarily for uniprocessor configurations. Their relationship is akin to that between the present Athlon and Duron microprocessors in that respect. AMD has announced that the release of these processors is imminent, and has given them the brand names Athlon 64 (Clawhammer) and Opteron (Sledgehammer).

The Hammer processors all have 40-bit physical address space, allowing them to easily handle 1 terabyte of RAM and 48 bits of virtual address space, for 256 terabytes of total addressable memory. The architecture has added 8 more integer registers to the traditional 8 in the old IA32 architecture, in addition to extending the registers to 64 bit width, and has support for SSE and SSE-II floating point instructions.

The processors have an integrated memory controller capable of interfacing to DDR SDRAM and RDRAM easily, which is supposed to reduce latency on memory accesses significantly. The Hammer processors also include HyperTransport technology, providing high-speed, low latency point-to-point links. The Athlon 64 (Clawhammer) is supposed to have a single HyperTransport link with a bandwidth of 6.4 gigabytes/sec, while the Opteron (Sledgehammer) would have three links, with a total maximum bandwidth of 19.2 gigabytes/sec. The single HyperTransport link on the Athlon 64 would be intended for connections to the system bus of a computer incorporating it, while two of three HyperTransport links on an Opteron might be used to link to other processors, making construction of a powerful multiprocessor system simple. Initial clock speeds for these processors are in the 800 MHz to 1 GHz range.

AMD has announced that systems incorporating this architecture should hit the mass market by the first quarter of 2003.

Update (January 20, 2003): A quick look at AMD's website shows that the Sledgehammer and Clawhammer codenames have been given the official brand names AMD Opteron and Athlon 64 respectively.


Anand Lal Shimpi, "The AMD Hammer Architecture: Making Sense of it All", at .com/cpu/showdoc.html?i=1546&p=1

Anand Lal Shimpi, "AMD's Hammer in Action: The Most Impressive Demo of IDF",

Fred Weber, "AMD's Next Generation Microprocessor Architecture," at,,30_118_4699,00.html

"THG Visits AMD: The First PCs With the Hammer CPU",

"AMD Opteron Processor Frequently Asked Questions",,,30_118_4699_7981%5E7987,00.html

"HyperTransport FAQ"

Registers in AMD's Hammer Architecture

A lot of people have wondered, just what is in the Hammer architecture that's going to revolutionize computing? What makes the processor 64 bit? And for those who know something about computers, the eternal question is, are we finally going to get away from the minuscule number of general purpose registers in the x86 architecture?

The answer is found easily in the AMD x86-64 Architecture Programmer's Manual, a five-volume set which AMD will ship you on paper and CD-ROM for free. Of course, you can download it as well.


x86 16 bit     x86 32 bit     x86-64
AX             EAX            RAX
BX             EBX            RBX
CX             ECX            RCX
DX             EDX            EDX
DI             EDI            RDI
SI             ESI            RSI
BP             EBP            RBP
SP             ESP            RSP

On 16 bit x86 intel CPUs (8080 through 80286) you have eight GPRs (general purpose registers) to work with. In practice, only four of them are actually general purpose because the others are used for addressing. Assuming you are doing both source and destination addressing at the same time, this ties up DI and SI. SP is your stack pointer and so it is generally not available for your use, and BP is a secondary stack pointer often used for addressing data. Realistically this leaves us with four 16 bit general purpose registers: AX, BX, CX, and DX. Each of these can be addressed as two eight bit registers; AH and AL (high and low), BH and BL, et cetera.

32 bit intel CPUs have 32 bit general purpose registers; No more of them, but they are all twice as long. You may alter AX without altering the high 16 bits of EAX.

x86-64 defines 64 bit general purpose registers, in addition to defining eight completely new registers, R8 through R15. Unlike the A-D registers, these cannot be broken up into smaller pieces of 32, 16, or 8 bits, and they are only available in x86-64 native mode.

     64                                                             1
BIT  4321098765432109876543210987654321098765432109876543210987654321
REG  RAX --------------------------->EAX------------>AX------------>|
REG8                                                 AH---->|AL---->|

The Hammer CPU has two modes; a "legacy mode" in which it acts like a 32 bit x86 processor, and a "long mode" in which it behaves as a 64 bit processor and applications have access to 64 bit registers. Legacy mode is divided up into real mode, virtual mode, and protected mode, which grant access to various registers and which imply the length of your GPRs. Long mode requires a 64-bit operating system; It will run 32 or 16 bit code in what it calls "compatibility mode". This is essentially equivalent to 32 bit intel CPUs going into real mode to execute 16 bit code; All of the registers look as if they were 16 or 32 bit registers to your program. This is made relatively trivial by the fact that there are generally different opcodes for versions of a processor instruction for different data sizes.

R8..R15 are not the only new registers in the x86-64 set, though they are the only new general purpose registers. Some other new registers are made available in 64 bit mode: XMM8..XMM15, eight new 128 bit "media" registers. The XMM0..XMM7 registers were created by intel for SSE/SSE2 instructions. AMD's Athlon XP processors emulate SSE; Hammer adds SSE2 support. SSE and SSE2 operations generally work on packed data, which is not formatted as a simple binary number. Sometimes they work on vectors, where there are multiple data elements in a single register.


  1. Advanced Micro Devices, Inc., AMD x86-64 Programmer's Manual Volume 1 - Application Programming. AMD, 2002.

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