Intel finally goes 64-bit like the other processors (see Sparc). Humorously enough, they knew they needed more memory space than 32 bits could afford but didn't want to confuse consumers by going all the way up to 64 bits yet, so the Xeon has 36-bit addressing. The codename for the IA-64 is Merced. Intel does not want to bring this chip to the consumer however, hoping to make a larger profit margin by only putting it in high-end servers.

Competely redesigned 64-bit ISA for Intel's next generation of processors, starting with the Itanium.

In 1992 Intel together with HP started designing Intel's first 64-bit Instruction Set. The team of engineers got a big leeway, the most important being: No hardware compatibility with IA-32.

The goal of this new architecture is to do away with all the limitations of the IA-32 design, which has been in use starting with the i386.

The Out Of Order execution has been greatly improved by using EPIC, this is a feature in the compiler that tells the processor which instructions can be safely run parallel. The processor reads a block of 128-bits, containing 3 41-bits instructions leaving 5 bits in which the compiler can put extra information.

The architecture also allows 1 instruction to be applied simultanious to multiple register.

Programs written for the IA-32 architecture will still run. The IA-64 design contains a translate which can translate IA-32 to IA-64 and back. But this process takes a lot, making the Itanium (the first processor to be build with IA-64) even slower than the Pentium I when running conventional programs.

Note: I am NOT a hardware expert. I just read an interesting article about this on and saw their was no good node about this in E2. Please let me know if you find factual errors or if you feel I left out important information.

IA-64 is not short for IndeterminAcy 64. It's the instruction set architecture of the new Intel Itanium processor.

The Itanium's i586 emulator

There are two ways a shift from one instruction set to another can be achieved: recompile or emulate. The "recompile" option is available only for free software and shared-source software; the move from IA-32 to IA-64 will break legacy proprietary software compiled for IA-32. Thus, the Itanium processor (and possibly other IA-64 processors) contains an emulator that runs i586 (Pentium) code, but because (unlike in the Transmeta Crusoe situation) there is no additional RAM available to cache the results of a dynamic recompilation, it runs an interpretive core at the speed of an older Pentium. (At least it's better than the Pentium 4, whose narrow pipe to its dynarec cache puts the '4' (as in 486) back in Pentium 4.)

IA-64's stack

Registers r0-r31 of an IA-64 processor are similar to those in common RISC architectures. Registers r32-r127, on the other hand, contain the top 96 words of the stack and can rotate forward or backward. This can happen for three reasons:

  • When a value is pushed onto the stack, r127 is written to memory, the registers rotate forward one space, and the new value is written to r32. There are instructions to push more than one word at a time, which are typically used to create a stack frame.
  • When a value is popped from the stack, the value is read from r32, the registers rotate backward one space, and memory is read into r127. Again, there are instructions to pop and ignore several words to destroy a stack frame.
  • In a software pipelined loop, the registers move forward one space every cycle of the loop, so that one cycle of the loop can pick up the results of the previous cycle without the dangers of exposed pipelines. Registers 32-127 must be saved prior to entering the loop and restored after the loop.

Disclaimer: I don't work for Intel or Hewlett-Packard, the developers of IA-64. This writeup may contain errors; /msg me with updates.


IA-64 is not a Nintendo game console unless Nintendo decides to use an Itanium processor in its next console after NINTENDO GAMECUBE. But that didn't stop me from designing this logo, roughly based on that of the Nintendo 64 console, presented in E2 ASCII Art:

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M      MM  a"       M   M      MM      M    a"    a" aa""      M
M      MM a"       M  aaM      MM      M    M     M""          M
M      MM M       Ma""  M      MM      M   M"                  M
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