Competely redesigned 64-bit ISA for Intel's next generation of processors, starting with the Itanium.

In 1992 Intel together with HP started designing Intel's first 64-bit Instruction Set. The team of engineers got a big leeway, the most important being: No hardware compatibility with IA-32.

The goal of this new architecture is to do away with all the limitations of the IA-32 design, which has been in use starting with the i386.

The Out Of Order execution has been greatly improved by using EPIC, this is a feature in the compiler that tells the processor which instructions can be safely run parallel. The processor reads a block of 128-bits, containing 3 41-bits instructions leaving 5 bits in which the compiler can put extra information.

The architecture also allows 1 instruction to be applied simultanious to multiple register.

Programs written for the IA-32 architecture will still run. The IA-64 design contains a translate which can translate IA-32 to IA-64 and back. But this process takes a lot, making the Itanium (the first processor to be build with IA-64) even slower than the Pentium I when running conventional programs.

Note: I am NOT a hardware expert. I just read an interesting article about this on and saw their was no good node about this in E2. Please let me know if you find factual errors or if you feel I left out important information.