SRAM, short for Static Random Access Memory, is a semiconductor memory device. It requires no refresh and is more stable than other forms of semiconductor memory. However, it does take up more area than DRAM.
BITLINE (bit) VDD BITLINE (bit_b)
| | |
| *---------*--------* |
| | | |
| |_ P1 P2 _| |
| _||o--* *--o||_ |
| | | | | |
*----------- ---------*------|----* | |
| A1 |__| Q | *----|------*---------- ---------*
| -- | | | | Q_b |__| A2 |
| | |_ | | _| -- |
| | _||---* *---||_ | |
| | | D1 D2 | | |
| | | | | |
| | *---------*--------* | |
| | | | |
| | VSS | |
| | | |
A1 - Pass Transistor 1; called an Access Transistor in this context
A2 - Pass Transistor 2; called an Access Transistor in this context
D1 - NMOS Transistor 1 of Inverter 1; called a Driver in this context
D2 - NMOS Transistor 2 of Inverter 2; called a Driver in this context
P1D1 - Inverter 1
P2D2 - Inverter 2
Q - Node at Output of Inverter 1
Q_b - Node at Output of Inverter 2
It is built using two inverters and two pass transistors. The inverters form a latch, which 'remembers' the stored charge via positive feedback. This is what keeps the memory intact and is the reason why a refresh isn't needed. SRAM cells operate in two phases, henceforth called phi1 and phi2. phi1 is when the BITLINEs are precharged, and phi2 is when the read or write operation occurs. A particular cell is selected for one of these operations by raising the WORDLINE to high.
Both BITLINEs are precharged to high (or 1) on phi1. On phi2, one of them gets discharged. Assume initially in phi1, Q is 0 and hence Q_b is 1. On phi2, WORDLINE is raised to high; Q_b and bit_b both remain at 1, but bit gets pulled down through D1 and A1, thus performing the read operation - bit now holds the value that was in the memory cell, namely 0. A similar process happens if Q is initially 1.
When bit is being pulled down, Q tends to rise; Q would normally be held low by D1, but the current flowing in from A1 causes it to rise. In other words, a read operation tends to want to change the existing value in the memory cell. As a result, the driver D1 must be stronger than the access transistor A1. This means that the transistors must be ratioed such that Q remains below the Switching Threshold of the P2D2 inverter. This constraint is called Read Stability.
Both BITLINEs are used to write the data. Assume Q is initially 0 and a 1 needs to be written to the cell. On ph1, bit is raised to high and bit_b is lowered to low (or 0). On phi2, WORDLINE is raised to high. Because of the Read Stability constraint, bit will not be able to force Q to high via A1. This means that the cell must be written to by forcing Q_b to low through A2. Once Q_b is lowered, D1 turns OFF and P1 turns ON, pulling Q to high. A similar process happens if Q is initially 1 and a 0 needs to be written.
When forcing Q_b to low through A2, P2 opposes this operation. In other words, the memory cell tends to not want to get updated with the new value. This means that P2 must be weaker than A2 so that Q_b can be pulled low enough to set the postive feedback into motion. This constraint is called Writability.
Source: CMOS VLSI Design 4th Edition, Neil H. E. West, David Money Harris