A Transmission Gate is a Digital Logic / Digital Electronics construct. It is a solution to the inherent problem of Pass Transistors. An NMOS transistor (see MOSFET) is a good conductor of Logic 0, but a bad conductor of Logic 1 (it is said to pass a weak 1). A PMOS transistor is a good conductor of Logic 1, but a bad conductor of Logic 0 (it is said to pass a weak 0). Refer to the writeup on Pass Transistors for a more detailed explanation of this.

 

                    _
S (NOT S, !S, ~S)
|
o
-------
------- PMOS Transistor
| |
INPUT --------- --------- OUTPUT
 | |
-------
------- NMOS Transistor
|
S

 

A transmission gate solves the problem by allowing the propagation of both Logic 0 and Logic 1. It does however have the disadvantage of taking up more silicon area. It is built by connecting the Drain of the NMOS to the Source of the PMOS, and the Drain of PMOS to the Source of the NMOS. The signals feeding into the Gates of each transistor are complements of each other.

In the circuit above, when S = 1 (or when S = VDD), the signal at INPUT passes through the gate to OUTPUT: If INPUT = 0, the PMOS transistor passes a weak 0, but the NMOS transistor passes a strong 0 forcing OUTPUT = 0; likewise if INPUT = 1, the NMOS transistor passes a weak 1, but the PMOS transistor passes a strong 1 forcing OUTPUT = 1. When S = 0 (or when S = VSS), both transistors are "off"; the gate does not allow INPUT to pass through, and OUTPUT is said to be floating.

A useful application of the transmission gate is a Tri-State Buffer whose outputs are connected to signal busses. It is also used to implement Multiplexers, and Exclusive OR / Exclusive NOR Gates.

Log in or registerto write something here or to contact authors.