Latches are one of the ways in which the Oracle database serializes access to shared resources. The differences between a latch and a lock:
  • Latches are normally very short lived, and are implemented by the hardware's test-and-set instruction. Locks cover longer-lasting operations, and are implemented in software.
  • Latches are waited for by spinning, testing the status of the lock a number of times in rapid sucession, sleeping, then repeating. The sleep time doubles (called "backing off") each iteration until a maximum is reached, then the process gives up trying to get the latch and reports an error. For this reason, latches are sometimes referred to as "spin locks". While waiting for a lock, the process is placed into a queue, and the code responsible for unlocking also transfers control to the next process waiting for the lock, which can yield all its processor time while waiting.
  • Latches are binary, they are either set or not. Locks have degrees of locked-ness, for example shared or exclusive.
  • Latches are specific to the local node, whereas locks are visible system-wide. An essential part of a VMS or Oracle cluster is the Distributed Lock Manager.

A third technique is the semaphore, devised by Dijkstra. They have two operations, increment and decrement, and can have any value that is positive or zero. Waiting processes attempt to decrement the semaphore, and processes that have finished using the resource increment the semaphore. If decrementing the semaphore would make it take a negative value, the process is blocked until the semaphore has been incremented. Oracle uses semaphores to communicate between processes, and for latch sleeps.

In a digital circuit, a latch is defined as a device that passes data from input to output when the clock is high (low) and holds the output fixed when the clock is low (high). When the latch is passing data, it is said to be transparent. Transparent-high latches and transparent-low latches are typically combined to make edge-triggered registers, which are the fundamental timing elements of most complex digital circuits.

There are several different types of latches; the clocked JK flip-flop is one example that has already been noded. Here I will give two simple examples of latches. The first is the pass transistor latch and the second is the C2MOS (clocked CMOS) latch.

Pass transistor latch

This latch is about as simple as it gets.


               CLK
                |
                |
             --------
             --------
             |      |       |\
  input------|      |-------|/°----output

The single NMOS transistor is called a pass transistor. When CLK is high, the input passes to the output (inverted). When CLK is low, the output remains fairly constant. However, the output gradually decays as charge on the inverter leaks away. For this reason, the pass transistor latch is called a dynamic latch. Since as-drawn the latch is being clocked continuously, loss of charge is not a serious problem. However if the clock were turned off to this portion of the circuit to save power (not common in most microprocessors), data would be lost after perhaps 1ms.

If a PMOS transistor were used, the latch would work the same except the latch would be transparent when the clock is low. As you might know (and if you don't, don't worry about it), PMOS transistors pass weak 1s, and NMOS transistors pass weak 0s. For this reason, the two are often put in parallel with eachother, and the resultant latch is called a transmission gate latch.

The inverter has two purposes. Its input gates act as capacitors that store charge (data) when the latch is closed. Also, since it is tied to the power supply, it can pull up or pull down its output nodes. This is critically important if two such latches are combined to make a register.

C2MOS latch

Although it might not be obvious, this latch is quite similar to the transmission gate latch. As just a latch, it's actually a bit inferior to the transmission gate latch. However, it has certain advantages when combined with another latch to make a register.


            Vdd
             |
            _|
  input  | | 
  ----- o| |  
         | |_
             |
   ___      _|
   CLK   | | 
  ------o| |  
         | |_
             |
             |--------output
            _|
   CLK   | | 
  -------| |  
         | |_
             |
            _|
  input  | |
  -------| |  
         | |_
             |
             |
            GND
              

When the clock is high, the input basically goes through an inverter (with some extra resistance due to the clock transistors). When the clock is low, the output remains fixed since the clock transistors are off. If the CLK and inverse CLK signals are switched, then the new latch becomes transparent when the clock is low.

The C2MOS latch is also dynamic. Static latches require feedback. Flip-flops are used to construct static latches.

Latch (?), v. t. [Cf. F. l'echer to lick (of German origin). Cf. Lick.]

To smear; to anoint.

[Obs.]

Shak.

 

© Webster 1913.


Latch, n. [OE. lacche, fr. lacchen to seize, As. laeccan.]

1.

That which fastens or holds; a lace; a snare.

[Obs.]

Rom. of R.

2.

A movable piece which holds anything in place by entering a notch or cavity; specifically, the catch which holds a door or gate when closed, though it be not bolted.

3. Naut.

A latching.

4.

A crossbow.

[Obs.]

Wright.

 

© Webster 1913.


Latch, v. t. [imp. & p. p. Latched (?); p. pr. & vb. n. Latching.] [OE.lacchen. See Latch. n.]

1.

To catch so as to hold.

[Obs.]

Those that remained threw darts at our men, and latching our darts, sent them again at us. Golding.

2.

To catch or fasten by means of a latch.

The door was only latched. Locke.

 

© Webster 1913.

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