The R-C circuit is a critically important model for both the switching delay and power consumption in a digital integrated circuit. In a digital integrated circuit, the channels of some MOSFET's drive the gates of other MOSFET's. More exactly, the first MOSFET's are resistive paths through which current must flow to charge or discharge the gates of the second MOSFET's, switching their binary logic states. Consider the diagram below. This circuit is a CMOS implementation of C = "A inverse" NAND B given two input signals A and B, but not A inverse. The inverter of A is on the left and the NAND gate is on the right.

        Vdd              Vdd        Vdd
          ^               ^         ^
          |               |         |
          |               |         |
        --              --        --
      ||              ||        || 
  A--o||         ----o||    B--o||
      ||        |     ||        ||
        --      |       --        --
          |-----          |         |
          |     |         |------------C
        --      |       --  
      ||        |     ||
  A---||         -----||
      ||              ||
        --              --
          |               | 
          |               |
         GND            --

Before the NAND gate yields the correct output, it must have both A inverse and B on its input gates. If both A and B arrive at the same time to the circuit above, then B will arrive to the NAND gate before A inverse because the inversion of A causes a delay.

The easiest way to approximate the delay of the inversion of A is to treat the situation as an R-C circuit. The resistor is either the inverter's PMOSFET or NMOSFET--whichever one is on. As a specific example, let's assume that the output of the inverter is initially Vdd, but then the input of the inverter switches from 0 to Vdd. This new input turns on the NMOSFET, which provides a conductive path from the output to GND.

Using semiconductor device physics, the effective resistance R of the MOSFET during this pulldown of the output can be easily calculated. Furthermore, the capacitance C of the two NAND inputs that the output of the inverter drives is known. The output can be modelled as an exponential decay with time, as derived in an earlier writeup. Typically the switching time for the inverter is defined the time it takes for the output to reach half its initial value. This switching time Τ corresponds to 0.69RC.

In a digital circuit, it's obviously advantageous to reduce switching delay as much as possible, since it ultimately determines the maximum possible clocking rate for the circuit. Therefore less resistive MOSFET's with smaller input capacitances are highly desirable. The best way to achieve this combination is to reduce the size of the MOSFET's. The size of MOSFET's has decreased by orders of magnitude over the past decades and microprocessors have gotten faster (see Moore's Law). It is important to note that other resistances and capacitances besides those mentioned must be taken into account. Examples of such "parasitic" resistances and capacitances are interconnect resistance and capacitance, drain-to-body capacitance, and series resistance.

The R-C circuit also offers a way to analyze power consumption in a digital circuit. Typically, the vast majority of power consumed in a microprocessor is due to the charging and discharging of MOSFET gate capacitors. So how much energy does it take to charge a capacitor? If you remember some physics, you might be inclined to say 1/2CVdd2. This number is the energy stored in the capacitor. However, charging the gate capacitor requires current through a MOSFET channel, which we modelled as a resistor. It can be shown (very straightforward calculus) that the energy lost due to heating of the resistor also equals 1/2CVdd2. Thus the energy required to switch the binary state of a node is CVdd2. To get this in terms of power, we can multiply by the number of times the node switches per second. This is written as the clock frequency f times an activity factor α that describes the probability of switching. We find that the power required to operate that node is αfCVdd2.