D-type flip-flops have a larger truth table than shown above. This is how they function:

```
Standard 1/2 of a 4013 chip

(S)
Set
|
|
_______|_______
|               |        Truth Table
D    |               |   Q    -------------_-----------
----|               |----     D   CL  Q   Q   S   RST
|               |        -------------------------
|               |         1   ^   1   0   0    0
|               |         0   ^   0   1   0    0
|               |         X   X   1   0   1    0
|               |   _     X   X   0   1   0    1
CL   |               |   Q    -------------------------
----|               |----     X = Does not matter.
|               |         ^ = Signal transition
|_______________|             low-to-high.
|                 1 = High (voltage)
|                 0 = Low (ground)
|                 Q = Normal output
Reset               D = Data In
(RST)               CL= Clock signal
S = Force set condition (Q high)
RST = Force reset condition (Q low)

```

A high signal on SET will cause the flip-flop to set Q high. A signal on RST will cause the flip-flop to set Q low. These two signals override anything currently on the flip-flop, and it does not matter what is happening on the CL or D lines.

The signal comes in on D. A different signal coming in on the Clock (CL) line will tell the chip to take the signal on the D line and place it on the Q (output) line. Some circuits need to take the opposite of the signal coming in on the D line, so the flip-flop also has an output that works opposite of the normal Q. It is called the NOT-Q, and shown with a bar over the Q; see the truth table and diagram for an example.