The MIPS R8000 is a curiosity in the world of microprocessors. It was the only RISC CPU implemented as a chipset rather than a single chip, with its integer-math unit and its floating point unit in separate physical packages. Unlike Intel's 80386 with its 80387 FPU, the R8000 by necessity consisted of both chips.

It had 4MB of external L2 cache, which actually acted as the L1 data cache for the FPU. The integer unit, however, had 16kB of integrated instruction cache and a further 16kB of L1 data cache. Because of its decoupled design and unusual cache architecture, clock speed was severely limited in the R8000. Most R8000 CPUs were limited to 75MHz, though a few were clocked up to 90MHz. Despite its low clock speed, the R8000 was usually faster than the MIPS R4400 for floating point math, often by a large margin. It was not a spectacular performer on integer-heavy code, however.

It saw little use. The 75MHz R8000 was used in SGI's Indigo2 workstation, Onyx visualization and Challenge L server system, while the 90MHz version was used in the Onyx and Challenge L only. A proposed 90MHz Indigo2 was canceled with the introduction of the faster and easier to manage MIPS R10000.

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