CAS stands for 'Column Address Strobe'. While bits in a modern DRAM chip are still arranged in a grid, there are so many bits that they can't feasibly have one pin for the row and column address anymore (a 256 megabit DRAM, for instance, has a 16384x16384 grid of bits, requiring 28 pins per chip to select the address). Instead, the required column and row are passed in one at a time over serial address lines, synchronised to a clock (the strobe).

When a DRAM is accessed, the Column Address is Strobed in, causing the DRAM to read the entire column into a static ram buffer (or latch). This is necessary as reading a DRAM bit discharges (and hence erases) it, and the data must be written back in. The Static ram latch does not have this problem.

The Cas Latency is the time the DRAM chip takes to read the data from the DRAM array into the column buffer, and hence be ready to accept the Row Address Strobe, which causes it to send data from the buffer to the data bus. If the Row Address Strobe is sent too early, the data in the buffer may not be what was stored in the DRAM. The write process is more complicated, but CAS latency plays a similar role.

The effect of a high CAS latency is somewhat mitigated in modern (EDO or later) DRAM, as data may be kept in the buffer, and one CAS can be followed by multiple RA Strobes, retrieving several bits for one CAS latency.

Most most modern motherboards can retrieve from the DIMM the highest reliable CAS latency, but many allow the user to override this. CAS latency is usually measured in clock cycles, so a 3C latency 133MHz DIMM has a latency of 2.25C when run at 100MHz.