Sorry to burst your bubble, but on probably 99% of the instruction sets out there... most RISCs included...

PC/IP isn't a normal register.

And, in fact, JMP xx is the "load $PC xx" instruction. And BRA xx is the "add $PC xx" instruction. Any assembler which allows you to do these things would probably just emit JMP/BRA instructions (or their equivalents) in the instruction stream.

Also, your little event loop completely disregards all of the things which make CPUs fast these days - prefetch caches, pipelines, instruction scheduling/reordering, dynamic recompilation (believe it or not, but most CPUs these days, RISC and CISC alike, internally recompile stuff into a completely different representation; the Athlon and Crusoe, for example, recompile x86 CISC into native VLIW formats (as a generalization in the case of Athlon, anyway)), and so forth.

And there's a very good reason the PC isn't a normal register. Even single-cycle RISC and VLIW setups have a state machine inside, with some very precarious timing with bus lines and clock signals and so forth.

To make PC a normal register would be a huge performance hit, and for what gain? So you can multiply it or something? When would that even be a conceivable operation except in the most esoteric of cases?

By your own admission, your view was extremely oversimplified. It was also extremely naive, considering that jump/branch instructions are simply load/add instructions specific to the PC which allow the CPU (as a whole) to work out the whole juggling act of pipelines and scheduling and the like.

Sageran: stack machines suck. There have never been any clear examples of a stack machine being even remotely as efficient as the most basic RISC, simply because either you have a very small stack in the CPU (see the 8087 for why that sucks) or you keep your stack in some external memory, which will be slow, just like if you had - get this - a normal braindead accumulator architecture. And we all know how fast the 6502 is.

The argument that "stack machines are better than pipelined machines because you don't have to pipeline them" is total bull. Stack machines can't be efficiently pipelined (since everything inherently causes read/write hazards), but that doesn't make it inherently faster! That's like saying "A bicycle is faster than a Ferrari because you can't put in a faster engine." There are many real-world examples of stack-based instruction sets being pipelined, yes (see JIT Java compilers as executed on the host CPU, or the Athlon's implementation of the 8087), but internally the CPU is certainly not stack-based. As far as "fetching a whole block of instructions at once," that's what's known as a "prefetch cache," and that's not something exactly unique to stack-based machines. :)

pokey: Yes, I know the PC is a register. But it's not worth the overhead to make it addressable as a normal register - that is, it's a special register. Yes, the circuitry for storing the value is the same, but that doesn't mean the path leading to the circuitry is. Also, I was rambling about JMP being load (MOV) and BRA (by which I meant - even if I didn't say - all the conditional branch operations, not just BRanch Always) being add (ADD), only in generic RISCy terms, so one would think I already said what you did. ;) Or were you replying to Sageran?
pokey: Oops, sorry. :)