The PCI Express Architecture defines a flexible, scalable, high-speed, serial
, point-to-point, hot pluggable/hot swappable interconnect that is software-compatible with PCI
The foundation of the PCI Express Architecture was laid in the Arapahoe Working Group under the code name Third Generation I/O
(the first two generations being the ISA
buses). In early 2002, it was re-named the PCI Express Architecture.
Key features of the PCI Express Architecture Base Specification are:
- Compatibility with current PCI enumeration and software device driver models.
- Each point-to-point interconnect may have 1, 2, 4, 8, 12, 16, or 32 dual simplex 2.5 Gbps lanes (2.0 Gbps effective rate), providing scalable bandwidth to 128 Gbps (16 gigabytes/second) between nodes.
- Predictable latency to enable applications requiring isochronous data delivery.
- Native Hot Plug/Hot Swap capability.
- Native Power Management capability.
The PCI Express Architecture is intended to replace AGP
. The first generation of PCI Express Architecture provides twice the bandwidth of AGP8X. Additionally, the PCI Express Architecture supports multiple graphics I/O devices in a single system.