Recently announced at an Intel shareholders meeting, Itanium 2 is Intel's official release name of the McKinley processor. The Itanium family runs the IA-64 instruction set, which is known for being an adaptation of EPIC an ISA that uses Very Long Instruction Words (VLIW) to exploit instruction level parallelism (ILP). Itanium 2 will completely support code that runs on Itanium chips, so no recompile of old code or applications is neccesary. The Itanium 2 is due to be released sometime late 2002 or early 2003.

Intel is using the new name with the number 2 probably to distinguish McKinley processors from the earlier and much despised Itanium processors known as Merced inside Intel. Itanium was such a flop that a new name is needed as a fresh start for the McKinley chip, which supports many small yet vital improvements which will improve performance by 1.5 - 2.0 times that on Itanium. The most important improvements include a smaller pipeline and better memory system so that branch mispredicts, cache misses, and page faults do not stall the system nearly as long.

Brief Facts

System Bus
  • 128 bits wide
  • 200 Mhz/400 MT/s
  • 6.4 GB/s*
  • 2 bundles per clock
  • 6 integer units*
  • 2 floating point units
  • 328 total registers
  • 2 loads and* 2 stores per clock
  • 11 issue ports
  • L1 - 2 X 16 KB - 1 clock latency*
  • L2 - 256K - 5 clock latency
  • L3 - 3MB - 12 clk latency
  • 32 GB/s bandwidth


Here are some benchmarks from the mouth of The Devil himself versus Sun Microsystem's UltraSPARC III. These numbers came from a marketing handout, which surely wouldn't contain any benchmarks that showed the Itanium in a bad light whatsoever.

SAP 2-tier SD
470 - Itanium
420 - UltraSparcIII

1520 - Itanium
568 - UltraSparcIII

3.5 - Itanium
1.8 - UltraSparcIII

3700 - Itanium
891 - UltraSparcIII

MCS.Nastran - Nastran 2001 xltdf
2.12 - Itanium
1 - UltraSparcIII

See McKinely and Itanium for more information.

Log in or register to write something here or to contact authors.