In digital logic, devices ideally have only two states: high and low, representing the logical values 0 and 1. This is exactly why they are digital devices. However, we live in an analog world and issues including unintended capacitance, ground loops, and brown outs can cause variations from the ideal voltage levels.

For instance, a device may expect 5V to represent a logical 1 and 0V to represent a logical 0. The noise margin is the amount of deviation from these ideal values that is acceptable for normal operation of the device. The same 5V device may have a high noise margin of 2.6V, causing it to register a high value with any voltage level between 2.4V and 5V. It may also have a low noise margin of 0.9V so it will see a low for any voltage level between 0V and 0.9V. High and low noise margins may not be so disparate, but it depends entirely on the implementation technology, (e.g. TTL, PMOS, NMOS, CMOS, ECL).

If a voltage level falls outside of both noise margins, the resulting output from the device is undefined. Further, if voltage levels exceed the logical high or low, permanent damage to the device may result.

As an aside, it's worth noting that a high voltage level may correspond to a logical low. (5V = 0, 0V = 1) This is referred to as negative logic. The high noise margin generally refers to the noise margin at the higher voltage level, regardless of whether positive or negative logic is used.

Log in or register to write something here or to contact authors.