PowerPC 601

The PowerPC 601 was the first (1993) implementation of the PowerPC microprocessor architecture, manufactured by IBM. It is basically a modified one-chip IBM POWER processor core with a bus interface designed by Motorola. There has also been a low-power version of the 601 called the 601+.

Summary of features:

• 32-bit PowerPC implementation, 64-bit data bus, 32-bit address bus
• up to 110Mhz clock speed (601+)
• three execution units: one integer unit, one floating-point unit (with a single precision multiply-add pipeline), one branch processing unit
• 8-stage instruction prefetch queue
• 32KB 8-way set-associative on-chip unified instruction/data cache
• memory management unit with 256-entry 2-way set-associative unified translation look-aside buffer
• supports 29 instructions and 1 register (MQ) that are part of the POWER but not of the PowerPC architecture definition
• implements two real-time clock registers (seconds and nanoseconds) that are also not part of the PowerPC architecture
• supports multiprocessing using the MESI protocol for maintaining cache coherence