Electronics Terminology: BIST
In electronics, BIST stands for Built-In Self-Test.

Built-In Self-Test is a technique commonly used in production testing of microchips. As the name suggests, a device incorporating BIST has the ability to conduct a test of itself, as opposed to using an external 'Automated Test Equipment', (ATE), to carry out the test.

Using BIST techniques allows internally-generated test pattern to be run "at-speed", i.e. at the operating frequency of the device as opposed to a frequency dictated by the tester, (which is usually lower). Also, less tester pattern memory is required since the test patterns are generated internally. BIST is also useful for testing structures deeply embedded within the circuit, which are hard to access from the device's I/O pins.

On the downside, BIST logic does take up a certain amount of real estate. It may also impact the non-test performance of your design too.

The most common application of BIST techniques in chip testing is memory BIST, where an internal pattern generator, (BIST 'engine'), is used to test embedded memories. Given certain limitations, one BIST engine can be used to stimulate several memories concurrently, further saving test time. Using BIST techniques to test such on-chip memories removes the need to allow access to their inputs and outputs from the 'top-level' of the design, which increases complexity.

A generic BIST implementation typically incorporates some kind of pattern generator. Memory BIST uses one of several industry-standard RAM test algorithms. BIST used to test random logic uses stimulus created by a pseudo-random pattern generator, (typically an LFSR). In addition, some kind of logic to capture the response of the 'circuit-under-test' is included. This is usually a form of CRC circuit, called a MISR, which captures the circuit's response during the duration of the test and generates a test 'signature' which can be used to determine a pass or fail. Finally, some kind of control logic is employed to oversee the pattern-generation and response- analysis logic.

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