On PowerPC architecture, the "eieio" instruction is used enforce instruction execution in order, that is, to prevent the pipelines from executing instructions in a different order than they were intended, typically used in combination with instructions that are doing memory mapped I/O. I've heard (and it sounds reasonable, but I don't know for sure that it's true) that the opcode used for the eieio instruction is the same as a NOP on earlier versions of the processor that didn't have the capability to execute instructions in parallel. That is, they made the NOP instruction do something on the PowerPC.