a
 
f b
 
g
 
e c
 
d
dec BCD 2^  Output
3 2 1 0 
W X Y Z  a b c d e f g
+
0 0 0 0 0  1 1 1 1 1 1 0
1 0 0 0 1  0 1 1 0 0 0 0
2 0 0 1 0  1 1 0 1 1 0 1
3 0 0 1 1  1 1 1 1 0 0 1
4 0 1 0 0  0 1 1 0 0 1 1
5 0 1 0 1  1 0 1 1 0 1 1
6 0 1 1 0  1 0 1 1 1 1 1
7 0 1 1 1  1 1 1 0 0 0 0
8 1 0 0 0  1 1 1 1 1 1 1
9 1 0 0 1  1 1 1 1 0 1 1
A 1 0 1 0  1 1 1 0 1 1 1
B 1 0 1 1  0 0 1 1 1 1 1
C 1 1 0 0  1 0 0 1 1 1 0
D 1 1 0 1  0 1 1 1 1 0 1
E 1 1 1 0  1 0 0 1 1 1 1
F 1 1 1 1  1 0 0 0 1 1 1
Yes, it is quite easy to make a little
ROM with a few
bytes  and
frequently that is what is used. Yet, it is also interesting to sit
down and work out the
logic for the
gates that would be
necessary to produce such an
output.
\YZ output: a
\ 
WX \ 00 01 11 10
+++++
00  1 0 1 1

01  0 1 1 1

11  1 0 1 1

10  1 1 0 1

In designing the circuit for the output of 'a', the above
Karnaugh map is consulted. There are some patterns in there to simplify the logic necessary. For example: if the bits 'YZ' are 10, then the result is true  no matter what the other values are.
Form this point on, the capital input refers to a '1', and lower case input refers to a '0'. Thus  'YZ' is '11' and 'Yz' is 10. Furthermore, the logical 'or' is represented by '+' and logical 'and' is represented by multiplication. Just as with math notation 'x*y' can be written as 'xy', so it can be here too.
The output for 'a' begins with:
Yz
Squares are also useful, and realize that they can wrap around the edges. The square: Wz also covers some in the lower half wrapping around the edge.
Yz + Wz
The other squares that exist are: Yw and XY. Although it almost escaped me, there is another square too: 'zx'. This one is the four outermost corners.
Yz + Wz + Yw + XY + zx
There are some stragglers that are not possible to get into a square or run of 4. Three inputs are necessary to cover them. The fewer inputs the better. These are the locations at yZwX and yZWx. By pairing them with an adjacent '1' one of the inputs can be removed.
a = Yz + Wz + Yw + XY + xz + ZwX + WXy
This reads:
Segment 'a' is to be lit up if any of the following is true:
 Y is true and Z is false.
 W is true and Z is false.
 Y is true and W is false.
 X is true and Y is true.
 Z is true, W is false, and X is true.
 W is true, X is true, and Y is false.
From this point onward, it is left as an exercise to the reader as it would be a waste of nodegell to go through an extensive explanation of the logic behind the remaining 6 outputs of the BCD to 7 Segment integrated circuit. Following the above method of identifying the largest sets of adjacent '1's should make the simplest possible circuit necessary.
This node has been brought to you by Node Your Homework  the
above problem was an assignment for ECE 352  a class I took in 1992.