Scalable Processor ARChitecture. Or a really fast chip produced by Sun Microsystems, which most people would use if they could get their hands on it. Well, I would anyway.

The older sun4 type machines are very cheap these days and can be had for minimal cash. However, they are still very useful. A sparc 1 can be used as an effective Xterminal. They are ideal for this task as they come with ethernet built in and can run Linux or another version of Unix. Also, some very high quality fixed-sync Sun monitors are available for them very cheap also, which makes for a very easy to use yet inexpensive solution. A good place to find them in Boston is at the MIT swap meet.

A little history, back when RISC was the up and coming thing, SUN wanted one, but no one had one for sale. So they made one up. Originally known as Sun Processor ARChitecture, it was not actually a chip per se, but a specification (SUN not owning fabrication plants). Several chip manufacturers, notably Texas Instruments and Cypress (later Ross Technologies) actually produced the chips.

Bill Joy from Sun and Dave Patterson from Berkely started work on the SPARC architecture in 1984. In 1986 they produced they the version 7 spec (32 bits) which was then made into the first line of SUN workstations, the SUN 4/xx0 line of workstations.

The line has been updated several times over the last 18 years. SuperSPARC and SuperSPARC-II is a superscalar version of the original 32 bit CPU. Ross produced the hyperSPARC which had a faster clock (200Mhz vs. 85Mhz in the SuperSPARC). Also the microSPARC was produced (being a cheaper, less powerful cpu similar to Pentium vs. Celeron or Athlon vs. Duron)

Finally there are the 64 bit versions. SPARC64 produced by Fujitsu (who actuall owned Ross for awhile) focused on out of order execution as opposed to Sun's chosen one, the UltraSPARC. The UltraSPARC did not do out of order execution arguing that memory latency would negate the benefit. What it did add though was a set of graphics operations (like MMX or HP's MAX on their PA-RISC).

The SPARC, or Scalable Processor ARChitecture, is a RISC architecture designed at UC Berkeley in the mid 80s, primarily by David Patterson. The original version was called the RISC I, which is thought to be the first VLSI RISC CPU design.

The design was picked up by Sun, who was shopping around for a new CPU to create a new line of workstations with, replacing the Motorola 68k processors that the early Sun machines were built on. The first commercial SPARC-based machine was the Sun-4, released in 1987, and Sun continues to market and sell systems built on variations of the SPARC architecture, though they also sell machines based on various x86 and x86-64 CPUs.

The SPARC is in most respects a classic load/store RISC architecture: 32 integer registers, 32 floating point registers, and hardcoded /dev/null register. The first widely used version, v7, didn't even include a multiply instruction, just a simple multiply helper instruction from which a compiler could synthesize a multiplication. This was a case of the SPARC being a little too RISC for it's own good; for certain operations, specifically public key crypto, you need to do a lot of multiplications, which is why opening up an SSH or SSL connection with a SPARCv7 machine (or a later machine running code compiled for v7) takes forever, as the CPU grinds through the multiplications. This particular failing was fixed in the v8 architecture; in fact the only changes between v7 and v8 were the addition of multiplication and division instructions.

One interesting thing about the SPARC design is register windows. The basic idea is that the system can provide an nearly arbitrary number of actual hardware registers, and it cycles through sets of them during function calls (this is only visible to the operating system; user space code only ever sees 32 registers at a time). During design time, simulation had suggested that this would allow for better performance, but these simulations were flawed, because they did not take into account context switching. A typical machine will perform context switches dozens or hundreds of times a second, and as the number of registers increase, the context time becomes more and more expensive.

The SPARC v9 architecture adds 64-bit registers and operations, and was marketed as the UltraSPARC by Sun. This is an evolutionary upgrade, and in fact aside from the larger address space few programs take advantage of the features v9 offers. The other additions include adding more floating point registers as well as 128-bit floating point operations. In current systems the quadword floats are not implemented in hardware, but are emulated by the operating system, so the performance hit negates most of the advantages. Some of the changes were made to support more advanced operating system constructs or to support high-end hardware with hundreds or thousands of CPUs, so they won't be seen outside the implementation of the kernel or libc. One interesting addition was VIS, which adds a handful of SIMD instructions, but outside of Sun-written software nobody uses it. Compared to MMX/SSE, VIS is extremely limited, more in line with the Alpha's MAX extension.

SPARCv9 has the deficiency that while most instructions were extended to support 64-bit operations, there is no way to multiply two 64-bit words to get a 128-bit result. This is an oddity among 64-bit machines; nearly every other 64-bit architecture in existence supports this operation, and I have no idea why the SPARCv9 designers thought doing this was a good idea. This negatively affects the performance of crypto algorithms, especially public key crypto like RSA and Diffie-Hellman. This is because these operations rely on performing multiplication of large (typically 128 bit to 4096 bit) integers. If one integer is n words long, and the others is m, basic multiplication algorithms take about n*m operations. If you double the word size, you halve the number of words needed, so the multiplication takes only (n/2)*(m/2), or (n*m)/4, operations. This four-fold speedup is pretty noticeable, but this is difficult to do on the SPARC because of the lack of a full-word multiply instruction. You can synthesize such a multiplication out of 4 32-bit multiplies, but this hurts quite a bit; after normalizing for clock speed, a SPARCv9 is several times slower than an Alpha or Opteron at public key crypto. Someone at work theorized that this was so Sun would make more money selling SSL accelerator cards.

Since 1989 the actual SPARC instruction set architecture has been defined by SPARC International, a consortium of SPARC vendors, which is primarily led by Sun and Fujitsu, but also includes OEMs such as Texas Instruments, LSI, and Tadpole.

An amusing side note: Tim May, the raving paranoid cypherpunk, made the following claim in 1993

Sun Microsystems was ordered by the NSA to redesign their chips to capture keys, which is why the SPARC processor was introduced. SPARC stands for "Sun Processor Allowing Remote Capture."

Personally, I'm more worried about the orbital mind control lasers.


Sources:
http://www.cs.berkeley.edu/~pattrsn/bio.html
http://www.sparc.com/history.html
http://www.sparcproductdirectory.com/history.html


I would like to thank OldMiner for pointing out an error in an earlier version of this writeup.

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