The Motorola 68020 is a 32 bit microprocessor first debuted in 1984, making it the first commercially produced 32 bit CPU. It has been used as the basis for various systems from Sun Microsystems (sun3 architecture systems but not sun3x), Apple Computer (Macintosh II and LC), and Amiga (Amiga 2500 and 1200). It has also been popular as an upgrade for 68000-based computers because it is mostly bus-compatible and completely code-compatible with the 68000 (and, by extension, the 68010).

FEATURES

The MC68EC020 is a low-power (and slightly slower) implementation of the 68020 with a 24 bit address bus, giving it a 16MB address space.

DESIGN

A block diagram of the 68020 follows:


   +-----------------------+     +------------------------------------------+
   | Sequencer and Control |     | Instruction Pipeline          +--------+ |
   | +-------------------+ |     | +-----+   +-----+   +-----+   |Cache   | |
   | |   Control Store   |<========|Stage|<==|Stage|<==|Stage|<==|Holding |<===.
   | +-------------------+ |     | |  D  |   |  C  |   |  B  |<==|Register|<==.|
   |           ||          |     | +-----+   +-----+   +-----+   | (CAHR) | | ||
   |           \/          |     |                               +--------+ | ||
   | +-------------------+ |     +------------------------------------------+ ||
   | |   Control Logic   |============.                                       ||
   | +-------------------+ |         ||        +-------------------+          ||
   +-----------------------+   .==============>| Instruction Cache |<==~~======'
                               ||    ||        +-------------------+   ||  Internal
                               ||    ||                                ||  Data
                      .========='    `===========.                     ||  Bus
                      ||                        ||                     ||              32 bit
                      ||                        ||                     ||  +------+  |   data
                      ||                        ||                     ||  |      |--+--\ bus
                      ||                        ||                    //   | Data |--+--/
    A  32 bit         ||                        ||                   ||    | Pads |  |
   / \ address        ||   +--------------------||---------------+   ||    |      |
   | | bus            ||   | Execution Unit     ||               |   ||    |      |=====.
 --+-+--   Instruction||   |       .============  ============.  |   ||    +------+    ||
   | |         address||   |  .====||======~~===||=======.   ||  |   ||       /\       ||
   | |             bus||   |  ||   ||      ||   ||      ||   ||  |   ||       ||       ||
   | |         ____   ||   |  \/   \/      \/   \/      \/   \/  |   ||       \/       ||
+--+-+--+    /     +  ||   | +-------+    +-------+    +-------+ |   ||  +-----------+ ||
|       |   |      |==..=====|Program|    |Address|    | Data  | |   | =>|   Size    | ||
|Address|/--| MUX  /       | |Counter| .==|Section| .=>|Section| |   ||  |Multiplexer| ||
| Pads  |\--|      \       | |Section| || |       | || |       | |   ||  +-----------+ ||
|       |   |      |===.   | +-------+ || +-------+ || +-------+ |   ||       /\       ||
+-------+    \_____+  ||   |       /\  ||     /\    ||  /\       |   ||       ||       ||
    ||                ||   |       ||  ||     ||    ||  ||       |    \\      ||       ||
    ||                ||   |       `==========..========='       |     ||     | ========'
    ||                 \\  +-----------||-----------||-----------+     ||     ||
    ||                  \\             ||           ||                 ||     ||
    ||                   \\            ||           || +------------+  ||     ||
+----------------------+  `============ |           `=>|Misalignment|<= |     ||
| Bus Controller       |               ||              |Multiplexer |  ||     ||
| +-------+ +--------+ |               ||              +------------+  ||     ||
| |Write  | |Prefetch| |               ||                              ||     ||
| |Pending| |Pending | |               `================================'     ||
| |Buffer | |Buffer  | |                                                      ||
| +-------+ +--------+ |                                                      ||
|  ||  +--------+  ||  |<======================================================'
|  ||  |Microbus|  ||  |
|  `==>|Control |<=='  |
|      |Logic   |      |
|      +--------+      |
+----------------------+
          | |
          | |   Bus
        --+-+-- Control
          | |   Signals
          \ /
           V

REGISTERS

  • Registers D0, D1..D7 are 32 bit general purpose registers (GPRs).
  • Registers A0, A1..A6, as well as USP, ISP, and MSP are 32 bit address registers.
  • Register A7refers to the USP in the user privilege level and to either the ISP or MSP in the supervisor privilege level.
  • SSP is the active stack pointer in supervisor mode.
  • PC contains the address of the next instruction to be executed.
  • The 16 bit bit field register SR stores the processor status.
  • VBR contains the base address of the exception vector table in memory.
  • The alternate function code registers, SFC and DFC, contain 3-bit function codes (...) that optionally provide as many as eight 4-Gbyte address spaces on the 68020 or eight 16-Mbyte address spaces on the 68EC020.
  • CACR controls the on-chip instruction cache of CAAR stores an address for cache control functions.


References:

  1. Macintosh Systems: By Processor. Everymac.com, 2001. (http://www.everymac.com/systems/by_processor/68020.html)
  2. MC68020 MC68EC020 Microprocessors User's Manual. Motorola, 1992. (http://e-www.motorola.com/brdata/PDFDB/docs/MC68020UM.pdf)

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