A
RISC chip primarily achieves its instruction reduction through forcing all data to be in
registers. Whereas a
CISC chip has several different versions of the ADD instruction, depending on where the data is coming from (or going to)
registers or
main memory.
So, instead of just getting away with with providing
pointers to two numbers you wish to add together, you are forced to explicitly load the data into registers, and then execute the addition.
The
RISC model is not neccessarily faster than the
CISC model, however, the design of a
RISC chip is far simpler. And if it's simpler, the design's less likely to break when pushed harder; as well as being significantly cheaper to manufacture using more expensive fabrication methods.
Interestingly enough, where RISC architectures make operations register based, the
JVM, by going in the OPPOSITE direction, and doing away with user-accessible registers, also achieves a reduced instruction set. However few out there would DARE refer to a
Java machine as RISC.