You've heard of CISC
, which begat RISC
- but how about MISC?
MISC is minimal instruction set computing. It embodies many design ideals of the original RISC designs, as opposed to the, ahem, "RISC" designs like PowerPC/POWER that are common today.
A paper that describes MISC as used in the MuP21 microprocessor can be found at (http://www.ultratechnology.com/mup21.html). The MuP21 is optimised for Forth, so it is a stack machine. It has the following instruction set:
- Transfer instructions: JUMP, CALL, RET, JZ, JCZ
- Memory instructions: LOAD, STORE, LOADP, STOREP, LIT
- ALU instructions: COM, XOR, AND, ADD, SHL, SHR, ADDNZ (okay, so that will make IEEE floating point math interesting ;-) )
- Register instructions: LOADA, STOREA, DUP, DROP, OVER, NOP
It's a paucity of instructions, by modern standards. However, MuP21
was designed only a few years ago, and it's not a failed experiment by any means. The simple instruction set and presence of only three registers, T (top), A (address), and PC
, implies a bunch of nifty things:
- instruction length is only 5 bits
- MuP21 is implemented as a 40-pin DIP with a 20-bit memory and data bus. One fetch grabs four instructions. This allows the CPU to be clocked four times faster than memory.
I'm not doing this topic justice, so just go read the paper at the URL I gave above.
Why aren't MISC stack machines more common, if they look so good on paper? Well, programming them isn't something most people are used to. MuP21 was designed by Chuck Moore, who also designed Forth. Unless you're used to arranging things in a Forth kind of way, i.e. verbs first, nouns and so on following later, as modifiers, Forth will probably give you a headache if you try to write a large program in it. (supposedly, speakers of East Asian languages like Korean find Forth to be second nature. No wonder there's a culture gap ;-) )
MISC and extreme RISC designs also tend to be clock-bound. Since clocking chips at higher speeds is difficult, high-performance CPUs are starting to look pretty complex or at least very deeply pipelined as they try to cram every clock cycle with tasty computational goodness. Hmm, asynchronous logic, anyone?