What Is Asynchronous System Design?

Asynchronous system design, unlike synchronous design, does not use a global clock. Rather than asserting signals at a specific time for a specific duration, as synchronous systems do on the rising/falling edge of the clock, asynchronous systems assert signals after some event until another event. This technique allows asynchronous systems to be self-timed, they work to the average case performance, whereas synchronous circuits must be toleranced to worst case performance. It is also a natural way of describing systems with lots of concurrency as there is no need to plan all the possible interleavings. In short you only do the work you have to, when you need it. Synchronous circuits on the other hand perform work on every clock tick, whether it is needed or not. This gives asynchronous circuits, in theory, a number of advantages: lower power consumption, better EMC, faster execution. So why aren't all systems asynchronous? Well synchronising everything to a global clock makes things simpler, or it used to, now as VLSI density is increasing the problems of clock distribution are growing. This simplicity means that it is easier to come up with design techniques, and consequently design tools, for synchronous design and so it became the standard. Now though, asynchronous design is beginning to catch up as more research is done and new techniques are discovered.

How Do Asynchronous Systems Work?

Due to the lack of a global clock extra signals must be used to control the flow of data. A popular techniques is the request/acknowledge paradigm. Between two functional blocks, one called the initiator and the other called the receptor, are two controls wires, request and acknowledge, and a data bus. On top of these two wires are layered a signaling protocol, the two most commen being 2-Phase and 4-Phase.

2-Phase signaling uses a change in signal, either from low to high or high to low, to represent an event. This is the basis of its other names, event or transition signaling. There are two types of transfer that can be used, push and pull. In a push transfer the initiator sends data; in a pull transfer the initiator requests data. This is true for both 2-Phase and 4-Phase signaling and in both cases only the push transfer will be described. The initiator indicates that data is ready on the data bus by an creating event on the request line. The data on the bus will then be maintained until the receptor indicates that it has finished with it by creating an event on the acknowledge line.

4-Phase signaling differs in that an event is represented by the level of the signal, a high signal indicates an event. To allow this to occur the signal is always required to return to zero, leading to the name return to zero signaling. Due to the extra phases of 4-Phase signaling there are a number of additional options that determine when the data on the data bus is valid. The early, broad and late schemes all make the data valid at different times, only the early scheme will be described here. As in 2-Phase signaling the initiator indicates that data is ready on the data bus by an creating event on the request line. The data on the bus will then be maintained until the receptor indicates that it has finished with it by creating an event on the acknowledge line. The request line must then return to zero and finally the acknowledge line can return to zero completing the handshake.

Amulet

There is a lot more to asynchronous design than I have described and if you want to find out more you can visit the Amulet website (http://www.cs.man.ac.uk/amulet/). Amulet is an asynchronous implementation of the ARM architecture developed at the University of Manchester and shows what is possible with asynchronous system design.


For more information please see the clockless computing node.

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