A cache that contains page table entries. Given a virtual address a processor will examine the TLB, and if the desired page table entry is present (a TLB hit) then the frame number is retrieved and the real address is formed. If the desired page table entry is not found (a TLB miss), the processor uses the page number to index the process page table and examine the corresponding page table entry to form the real address. if the page is present in main memory then the processor can retreive the frame number from the page table entry to form the real address. The processor then updates the TLB to include this new page table entry. If the desired page is not in main memory, a page fault is issued. At this point, the operating system is invoked to load the page and update the page table.