SDF (thing)

Electronics Terminology: SDF

An SDF file is specific to a particular electronic circuit design and contains estimated timing delay information for all the logic gates, ("gate delay"), and associated interconnect, ("net delay"), in that design. SDF files are generated by analysis of the design netlist. There are two broad types of SDF:

• Pre-Layout SDF: Generated before design goes to layout. Gate delays derived from vendor library. Net delay estimated by drive strength of driving cell, capacitive load of inputs being driven and fanout.
• Post-Layout SDF: After layout of the design is complete, physical information relating to interconnect can be used to provide more accurate delay estimation.

This information, in conjunction with the design netlist itself, can be used to evaluate the timing performance of a design prior to manufacture. Such analysis can be conducted by "dynamic", (i.e. simulation), or "static", ("STA"), means.