ESD is a problem for IC's made using MOS/CMOS technologies, especially since the continual refinement of semiconductor manufacturing technology permits smaller and smaller transistors on an IC; smaller devices are more susceptible to ESD, even at a level which is 'invisible', or imperceptible, to humans.
Here's why ESD is so bad:

Sufficient build up of electrical charge on an MOS transistor's gate will cause the transistor's gate voltage to increase to the point where the gate oxide breaks down and provides a conductive path.

This breakdown of the insulating oxide layer in the transistor can cause catastrophic damage such that the IC stops working. Alternatively, the damage to the gate oxide may not have been catastrophic, but may have been sufficient to leave a leakage path in the material. Over time, the damaged gate oxide layer will deteriorate further until it eventually fails completely. So, even though a chip has sustained ESD damage, it may continue to function with no apparent problems for some time before failure: a reliability problem.

Measurement Standards

The electronics industry has several standards to measure an IC's resistance to ESD damage. Each recreates a common ESD damage mechanism:

  • HBM: Human Body Model - The most commonly used standard. Simulates ESD from a human by discharging a capacitor through a 1500 Ohm resistor.
  • MM: Machine Model - Simulates ESD from a metallic surface. Zero resistance discharge path.
  • CDM: Charged Device Model - Simulates discharging of a charged device through one of its leads.