A
netlist is a text file describing an
electronic circuit in terms of its
components and their
inter-connection.
A netlist can be created by hand or be generated as output from a synthesis or schematic capture tool. It is used for verification of both the timing and functional performance of the circuit. It is also used during the layout process.
Components in a netlist are labelled with an "instance name" to allow differentiation when the same component, (such as an "AND" gate, for example), is used more than once in a given circuit. The interconnect between components is referred to as a "signal" or "net". Each of these is also given a unique name.
Like the circuit they describe, a netlist can be either "hierarchical", (where components in the netlist "instantiate" further components themselves), or "flat", (where the netlist describes the circuit simply in terms of instances of "leaf cells" and their inter-connection).