The portion of a P6 microprocessor (or related derivatives: the Pentium II, the Celeron, and the Pentium III)which implements the core functionality of the implemented ISA. The P6 core implements the x86 ISA plus the enhancements it has evolved to include in a superscalar, OOO execution manner.

The core contains things like the ALUs, the Fetch and Decode units, and all other parts of the execution pipeline. Basically every part of processing.

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