is an approach used in electronics
to test CMOS integrated circuits
is based on measuring electrical current
, as opposed to voltage
. The technique exploits
the low power
drain characteristic inherent to CMOS
technology, (CMOS circuit
s only draw current
when they are changing state
will be 'conditioned'
into a pre-determined logic
state and then the circuit
is stopped. The easiest way of pre-conditioning is via the IC
's scan chain
s, (if it is a scan
based design). The theory is that the IC
will drain a very low level of current
in this quiescent state
. Any manufacturing defect
present in the
will likely cause the current
measured to deviate from the 'norm'.
The technique is seen as a valuable supplement to other methods of circuit testing since it allows the detection of certain
types of fault which might not be found using voltage-based techniques, (gate leakage within a transistor, for example).
IDDQ testing also allows certain otherwise 'untestable' faults to be
detected since it eradicates one of the two concerns of testability, namely observability: Any abberent behaviour within a
circuit does not need to be propagated to a device output in order to be detected - it will be evident in the quiescent current measurement made.