There have been several revisions of the BeBox hardware.
The first prototype, built shortly after the foundation of Be, Inc. in 1990, was based on a single AT&T Hobbit processor, a RISC chip designed to efficiently execute compiled C code.
The second prototype (1991) added a second Hobbit CPU and three AT&T 3210 DSPs for multimedia and communications applications. About 30 units of this model, which had proprietary expansion slots, were built.
When AT&T discontinued the Hobbit processor line in 1994, Be redesigned the BeBox based on the PReP specification, using the then brand-new PowerPC processor from Motorola and IBM. This dual-CPU machine with PCI and ISA slots is what most people now know as "the BeBox". Its first public presentation was on October 3, 1995 on the Agenda '95 conference.
The following are the most important revisions of the PowerPC BeBox:
- Rev.01 thru Rev.04 were prototypes and test boards. Only a few units were built of each, some of which were handed out to selected developers and press people.
- Rev.05 was the first publically available model, with two 66MHz PowerPC 603 CPUs. Over 400 of these were sold starting in January 1996. A peculiar feature of these machines is that they were shipped in a light blue case without a front bezel, because the design of the chassis was not yet finished.
- Rev.06, introduced in October 1996, finally had a neat-looking dark blue case and the famous blinkenlights. It also featured a larger BIOS flash ROM which was required for running BeOS DR9 and later versions. Owners of Rev.05 BeBoxen were offered an upgrade to the Rev.06 model, or to...
- ...Rev.07 and Rev.08 which featured two 133MHz PowerPC 603e processors. Apparently, there were some issues with the Rev.07 board and it was replaced with the updated Rev.08.
There was an early prototype of a quad PowerPC 604 machine, but in January 1997, Be discontinued the production of the BeBox, leaving the hardware business and focusing on the further development of the BeOS operating system, which they had ported to Apple PowerMac machines in late 1996.
The BeBox uses the Motorola MPC105 "Eagle" chip as its DRAM controller, PCI bridge and bus arbiter. This chip supports either two CPUs, or one CPU and up to 1MB of L2 cache. While it can handle SDRAM, the BeBox only accepts 72-pin 60ns FPM SIMMs (up to 1GB).
Apart from the processors and the host bridge, most of the BeBox consists of ordinary PC hardware (including standard PCI and ISA slots), augmented by some interesting I/O devices such as a Zilog microcontroller for low-speed infrared communications, and the GeekPort. Be usually shipped the machines with an S3 PCI VGA graphics card and an NE2000 ISA Ethernet card.
Be's decision to use the PowerPC 603 processor is interesting because, in contrast to the PowerPC 601 and the PowerPC 604 which were also available at the time, the 603 lacks nearly all features required for multiprocessing (it was probably chosen for its low price and power consumption; the CPUs in the 66MHz BeBox don't even have a passive heat sink). Cache and TLB coherency issues are handled in software using inter-CPU interrupts, and the missing PIR (Processor Identification Register) is emulated by one of the ASICs of the BeBox. The 603 only implements the M, E and I states of the MESI cache coherency protocol, meaning that the two CPUs cannot both hold the same cache line at the same time. This has the effect that a program using two threads that operate on the same set of data often runs much slower than the single-threaded version because the two CPUs waste most of their time playing cache line ping-pong. Together with the lack of a second-level cache, this makes the performance of the BeBox rather unimpressive (So what? It has blinkenlights, man!).