systems typically have a page table
with a list of virtual
s and their corresponding physical memory
locations. However, the page table resides in memory itself. The result is that to access a virtual memory address requires two memory accesses: one to the page table to find the physical memory address, and then a second to access the actual address. This is incredibly inefficient
A translation lookaside buffer (sometimes abbreviated TLB) is found in most processors with virtual memory support. It makes use of the fact that most programs typically only work on a small area of memory at once. When a memory address is accessed, its mapping is stored in a fully-associative cache inside the processor. The next time the same page is accessed, its physical mapping can be found quickly.
The translation lookaside buffer is the reason context switches can have big performance penalties. Every time the OS switches context, the entire buffer is flushed. When the process resumes, it must be rebuilt from scratch. Too many context switches will therefore cause an increase in cache misses and degrade performance. The buffer cannot be saved and restored as there is no guarantee in a virtual memory system that all virtual memory pages will exist in the same physical memory locations as they did before the process was suspended.