Amulets are a series of
asynchronous microprocessors designed by the
Amulet research group at the
University of Manchester Computer Science department. All processors are capable of executing the commercial
ARM instruction set architecture (ISA).
Amulet1 was the first design. Completed February 1993 the processor was the first asynchronous implementation of a commercial microprocessor architecture. Micropipeline design style used the 2-phase signaling protocol. Unfortunately due to the lack of a cache or on chip RAM the design was restricted by the external memory speed.
Amulet2 used moved to the 4-phase signaling protocol. The design included a 4Kbyte cache (rearangeable into a 8Kbyte RAM). The primary target for the design was low power consumption. A halt instruction can freeze the processor to use virtually no power while waiting for an interrupt. When completed in 1996 the chip boasted a performance of 42 MIPS. Both faster and with lower power consumption than the popular ARM7. When tested against the ARM6 the Amulet2 had a much lower harmonic noise emission, which is increasingly imporant in mobile telecomunications.
Completed in 2000, Amulet3i system on chip was designed to give better performance while keeping the low power properties of the prevous designs. The chip gave execution speeds of 120 (Vax) MIPS (equivilent to an ARM9). Additional to the core the chip held: on chip RAM, ROM, several synchronous peripherals and a DMA controller, all connected using a MARBLE / Chain asynchronous on chip bus.
Amulet microprocessors are capable of increasing or decreasing speed dependant on enviromental variables such as power supply or temperature. This can be seen in the Amulet and Rat experiment.