RISC - R
History and Basic Design
RISC was the general concept of CPUs that were deveoped in the late 70s and early 80s in several different projects that resulted in Stanford's MIPS, Berkeley's RISC 1 & 2 and the IBM 801. All RISC processors share several key elements being:
- One Cycle Execution Time: RISC processors have a CPI (clock per instruction) of one cycle.
- Pipelining: A techique that allows for simultaneous execution of parts, or stages, of instructions to more efficiently process instructions.
- Large Number of Registers: RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory.
RISC processors concentrate more on the software and as their name states, they have a reduced assembly language instruction set.
RISC vs. CISC
Today RISC is generally felt to be the right way to design processors. In fact, the i386 family are the last (at least major) CISC based processors.
CISC based processors take more into account of trying to get the job done in assembly in as few lines as possible. This may have been the more practical up until the 1960s. Now with much better compiler design, RISC is the way to go. In fact, in his book Only the Paranoid Survive, Andrew Grove wrote that the only reason Intel has not fully gone with RISC is because of compatability issues.
- Emphasis on hardware
- Includes multi-clock
- Memory-to-memory: "LOAD" and "STORE"
incorporated in instructions
- Small code sizes, high cycles per second
- Transistors used for storing complex instructions
- Emphasis on software
- Single-clock, reduced instruction only
- Register to register: "LOAD" and "STORE" are independent instructions
- Low cycles per second, large code sizes
- Spends more transistors on memory register