- Well suited for hardware implementation
- They can produce sequences of large period
- They can produce sequences with very good statistical properties
- because of their structure, they can be readliy anallzed with algebraic techniques

Definition

A LFSR of length L consists of L stages (aka delay elements) numbered 0,1,..., L-1, each capable of storing one bit and having both one input and one output; and a clock which controls the movement of data. During each unit of time the following operations are performed:

- the content of stage 0 is output and forms part of the output sequence.
- the content of stage i is moved to stage i-1 for each i, 1<=i<=L-1;
- the new content of stage L-1 is the feedback bit
*s*, which is calculated by adding together modulo 2 the previous contents of a fixed subset of stages 0, 1, ... , L - 1._{j}

Mathematical Fact:

if the initial state of the LFSR is {*s _{L-1}, ..., s_{1},s_{0}*} than the output sequence s = s

_{0}, s

_{1}, s

_{2}, ... is uniquely determined by the following recursion:

*s*mod 2 for

_{j}= ( c_{1}s_{j-1}+c_{2}s_{j-2}+...+c_{L}s_{j-L})*j*>=

*L*