binary multiples, eh?

Multiplying in binary is pretty darn straightforward. If you multiply something by 0, you get zero. If you multiply something by 1, you get the same thing back.

This can be utilized in the standard long division format:

0100
* 1011
0100
01000
000000
+ 0100000
00101100

Easy, no?


Note that shifting a binary number to the left or right by a digit is equivalent to multiplying or dividing by two, respectively. (just like shifting the decimal point left or right with base 10 multiplies or divides by ten).

(A first attempt at Nodeshell rescue...)

A 4-bit binary multiplier written in VHDL:

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity binary_multiplier is 
  port(CLK, RESET, G, LOADB, LOADQ: in std_logic;
       MULT_IN: in std_logic_vector(3 downto 0);
       MULT_OUT: out std_logic_vector(7 downto 0)	
);
end binary_multiplier;

architecture behavior_4 of binary_multiplier is 
  type state_type is (IDLE, MUL0, MUL1);
  signal state, next_state : state_type;
  signal A,B,Q: std_logic_vector(3 downto 0);
  signal P: std_logic_vector(1 downto 0);
  signal C, Z: std_logic;
begin
  Z <= P(1) NOR P(0);
  MULT_OUT <= A & Q;
  
  state_register: process (CLK, RESET)
  begin
    if (RESET = '1') then
      state <= IDLE;
    elsif (CLK'event and CLK = '1') then
      state <= next_state;
    end if;
  end process;
  
  next_state_func: process (G, Z, state)
  begin 
    case state is
      when IDLE =>
	if G = '1' then
	  next_state <= MUL0;
	else
	  next_state <= IDLE;
	end if;
      when MUL0 =>
	next_state <= MUL1;
      when MUL1 =>
	if Z='1' then
	  next_state <= IDLE;
	else
	  next_state <= MUL0;
	end if;
    end case;
  end process;
  
  datapath_func: process(CLK)
    variable CA: std_logic_vector(4 downto 0);
  begin
    if (CLK'event and CLK = '1') then
      if LOADB = '1' then
	B <= MULT_IN;
      end if;
      if LOADQ = '1' then
	Q <= MULT_IN;
      end if;
      case state is 
	when IDLE =>
	  if G = '1' then
	    C<='0';
	    A<="0000";
	    P<="11";
	  end if;
	when MUL0=>
	  if Q(0) = '1' then
	    CA := ('0' & A) + ('0' & B);
	  else
	    CA := C&A;
	  end if;
	  C <= CA(4);
	  A <= CA(3 downto 0);
	when MUL1 =>
	  C <= '0';
	  A <= C & A(3 downto 1);
	  Q <= A(0) & Q(3 downto 1);
	  P <= P - "01";
      end case;
    end if;
  end process;
end behavior_4;