PCI Express

Arapahoe (now PCI Express) is the (strange) name for Intel's new "third-generation" I/O technology for PC's, scheduled to replace PCI-X in 2003 and reach the majority of the desktop/home user market by 2009. This technology was previously named 3GIO for "third-generation I/O", and according to Intel, it will provide the kind of transfer speeds we will be needing when our computers run at 10 GHz or so.

The technology of today which Arapahoe seeks to replace is none other than that of our PCI cards, the add-ons that give more functionality, disk space, or whatever, to our computers. Today's PCI bus, operating at 66 MHz, can transfer a mere 266 Mbytes/second - PCI-X can do little over 1 Gbyte/sec, and it is currently only being used in expensive Compaq servers. HyperTransport, currently about to be rolled out by Advanced Micro Devices, Inc. (AMD) operates at a maximum of 12,8 Gbytes/sec - products based on it are expected in 2002, but the first one, the nForce chipset by nVidia is here already and is already making its way to motherboards.

nForce uses an 800 Mbytes/sec HyperTransport link to send data between its ICP and MCP, the two mainboard components which handle I/O and Multimedia - usually called the Northbridge and Southbridge. The high-speed link gives the nForce significantly higher performance than present-day chipsets by AMD, VIA and ALi.

However, Arapahoe-based products will likely be even faster when it finally arrives - already, Compaq have signed a deal with Intel to make use of the new technology.

A final note: Arapahoe is not, nor is it related to, InfiniBand, another Intel technology designed to provide connectivity between servers and other network devices.

The PCI Express Architecture defines a flexible, scalable, high-speed, serial, point-to-point, hot pluggable/hot swappable interconnect that is software-compatible with PCI.

The foundation of the PCI Express Architecture was laid in the Arapahoe Working Group under the code name Third Generation I/O or 3GIO (the first two generations being the ISA and PCI/PCI-X buses). In early 2002, it was re-named the PCI Express Architecture.

Key features of the PCI Express Architecture Base Specification are:

• Compatibility with current PCI enumeration and software device driver models.
• Each point-to-point interconnect may have 1, 2, 4, 8, 12, 16, or 32 dual simplex 2.5 Gbps lanes (2.0 Gbps effective rate), providing scalable bandwidth to 128 Gbps (16 gigabytes/second) between nodes.
• Predictable latency to enable applications requiring isochronous data delivery.
• Native Hot Plug/Hot Swap capability.
• Native Power Management capability.

The PCI Express Architecture is intended to replace AGP. The first generation of PCI Express Architecture provides twice the bandwidth of AGP8X. Additionally, the PCI Express Architecture supports multiple graphics I/O devices in a single system.

PCI Express addendum
With the inherent limitations in the original PCI interface having become apparent, PCI Express is proposed as the natural evolution of PCI that will take the PC industry into the next decade. PCI Express has been designed to provide a standard that can be used by different manufacturers that offers enough flexibility to accommodate desktop, notebook, server, workstations, embedded devices and mobile devices . This will simplify design, giving engineers an I/O standard that can be adapted to create 3D games on high-end workstations, or even used in notebooks and other mobile devices that require low power consumption. Another possibility is creating PCs that have a modular design, making it possible for some components to be separate from the PC case and motherboard. This would be ideal in offices or homes where workspace is at a premium.

The key to this flexibility is the scalable nature of PCI Express, as well as its serial nature. Whereas PCI sent data in parallel, PCI Express is constructed from 1 all the way up to 32 “lanes”. Each lane has contained a set of differential signal pairs, one pair for transmission, and another pair for reception. This “stackable” structure makes PCI Express extremely flexible, with PCI Express x1 offering 250 MB/s transfer rate and x32 offering up to 8 GB/s! For example, manufacturers can use x1 PCI express for applications such as gigabit LAN or SATA; although x1 has the least bandwidth of all PCI Express standards, it still has almost double the rate of the old PCI bus, and is more than adequate for most hardware implementations at the desktop level. Where PCI Express really shows its strengths is when multiple lines are stacked together, giving manufacturers and developers enough bandwidth to create powerful hardware and software for desktop PCs, notebooks, severs and workstations. Indeed, it can be said that finally, after all these years, PC I/O technology has caught up with the huge advances made in processor and memory technology.

Perhaps the most exciting advance will be the replacement of the AGP slot with a PCI Express x16 slot. PCI Express x16 offers a 4 GB/s transfer rate per directional lane (8 GB/s with both lanes), almost double the current AGP standard. Indeed, game developers, graphics card manufacturers and gamers themselves are eagerly anticipating this move to PCI Express x16 as the next evolutionary step for PC gaming. VGA cards using this slot are set to hit the market now, but don’t expect the games themselves to fully utilize the new technology for at least another year.