The D Flip-Flop is a very common sort of flip-flop (FF) that has only one input. It is constructed easily from the SR flip-flop:
      +------+          
D--+--|S    Y|---Q    clk D | Q
  _|_ |      |          _ --+--
  \_/ |  SR  |        _/_ 0 | 0
   o  |  FF  |        _/  1 | 1
   |  |      |
   +--|R     |
clk---|>     |
      +------+         

The D, like other sorts of FF's responds only on the active edge of the clock signal. See SR Flip-Flop. Unlike other sorts, however, the D has no rest state. On every clock cycle the FF must be either set or reset. This makes it ideal for storing the state of a state machine (since it changes on every clock pulse).

Multiple D FF's can be arranged in a bank to form a register, and thus are an important building block in many other components.

See also bistable multivibrator, SR Latch, SR Flip-Flop, JK Flip Flop, synchronous sequential network.

Also D-Flip-Flop.

D-type flip-flops have a larger truth table than shown above. This is how they function:


Standard 1/2 of a 4013 chip


             (S)
             Set
              |
              |
       _______|_______
      |               |        Truth Table
 D    |               |   Q    -------------_-----------
  ----|               |----     D   CL  Q   Q   S   RST
      |               |        -------------------------
      |               |         1   ^   1   0   0    0
      |               |         0   ^   0   1   0    0
      |               |         X   X   1   0   1    0
      |               |   _     X   X   0   1   0    1
 CL   |               |   Q    -------------------------
  ----|               |----     X = Does not matter.
      |               |         ^ = Signal transition
      |_______________|             low-to-high.
              |                 1 = High (voltage)
              |                 0 = Low (ground)
              |                 Q = Normal output
            Reset               D = Data In
            (RST)               CL= Clock signal
                                S = Force set condition (Q high)
                                RST = Force reset condition (Q low)


A high signal on SET will cause the flip-flop to set Q high. A signal on RST will cause the flip-flop to set Q low. These two signals override anything currently on the flip-flop, and it does not matter what is happening on the CL or D lines.

The signal comes in on D. A different signal coming in on the Clock (CL) line will tell the chip to take the signal on the D line and place it on the Q (output) line. Some circuits need to take the opposite of the signal coming in on the D line, so the flip-flop also has an output that works opposite of the normal Q. It is called the NOT-Q, and shown with a bar over the Q; see the truth table and diagram for an example.

D flip-flops are much like ice cream, they come in many different flavors. And regardless of the flavor you have, it's still a D flip-flop.

We are going to look at a simply D flip-flop first. The other flavors just build off the basic one.


            \Enable                
              |                    
       _______|_______            Truth Table 
      |               |           ----------------------
 D    |               |   Q        D  CLK  Q   \ENABLE
  ----|               |----       ----------------------
      |               |            H   ^   H      L
      |               |            L   ^   L      L
      |               |            X   L   Q      L
      |    74LS374    |            X   X   L      H
 CLK  |               |          ----------------------
  ----|               |            X = Don't care
      |               |            ^ = LOW to HIGH transition
      |_______________|            H - HIGH (voltage)    
                                   L = LOW (ground)
                                   Q = Output, CLK = Clock
                   

Three inputs and one output. Can it get any easier? Well, one input and no outputs but I don't know what the heck that would be.

Here's how it works. Q is going to output whatever value is on D right as the clock goes high. If the clock signal is already high when D changes the output does not change. Only when the clock signal is rising is there a change. This is what is referred to as a postive edge triggered D flip-flop.

And the truth table says all this and more, just not in so many words. It should also be pointed out that when the CLK is low, Q stays Q. Meaning, it keeps whatever value it has when CLK went from low to high.

But we have neglected the \ENABLE signal so far. When the \ENABLE signal is LOW, the D flip-flop works just as we described above. But when the \ENABLE signal goes high, Q will always be low, regardless of whatever D and CLK are doing.

May you have noticed how the \ENABLE signal works in the opposite way that one might expect. It would seem more intuitive for the D flip-flop to be enabled when it gets a HIGH signal instead of LOW. However this is not the case since the \ENABLE signal uses negative logic. (Normally you would draw a line over ENABLE, but here we will use a \ to depict negative logic.)

Think of it this way, when \ENABLE is HIGH the negative of it would be LOW. And if \ENABLE is LOW, the negative of that is HIGH. So a LOW on the \ENABLE signal really means a HIGH in a roundabout sortof way and the chip gets enabled.

There are other flavors of D flip-flops you can use, like those mentioned above. Some have SET and RESET signals. Others don't use a clock signal to set the value of Q but just a normal signal. (That truth table is subtly different.) Many have two outputs, Q and \Q. Where the \Q is always the opposite Q. (Remember that bit about negative logic?) But when it comes down to it, it's all just a way to take an input signal and hold it the output for a certain amount of time.

What can you do with D flip-flops? I thought you'd never ask. They can be used in shift registers, binary counters, frequency dividers, FIFOs and anything thing else you want to cook up.

This write up is based off the DM74LS273 datasheet.

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