After the technical success of the ARM1 and ARM2 processors, Acorn wasted no time improving the performance of their personal computer line. The first improvement, which came with the release of RISC OS, was to replace the original Archimedes seres with the new Archimedes A410/1 and A440/1, which featured improved memory performance due to the new MEMC1a memory controller. Following the success of these machines, they decided to focus on CPU core speed for their next computer, the A540/R260, and its diskless spinoff, the R225.
The initial ARM3 cores were released in 1989, and gave a performance of around 13 MIPS on average, compared to the 4 MIPS of the ARM2. Fundamentally, the most of the performance gains were due to the increased clock speed of 25MHz, and the addition of 4KB cache. These modifications were made possible by a new fabrication process at 1.5µm: even with the addition of a few features and the on-chip cache, the transistor count was still only around 300,000. This was remarkably compact, to the extent that Acorn had difficulty finding an integrated circuit package small enough to hold the ARM3 die.
The ARM3 was the first ARM processor to use cache at all. ARM elected to use a fairly simple caching model: a 64 way set-associative cache with random write through replacement method, and 128-bit cache lines. Alterations were made to the co-processor interface to support this, and the cache system was designated co-processor zero.
Another change made to the ARM2 instruction set brought the ARM series marginally away from the classical RISC philosophy, but allowed for the possibility of multiprocessing. The SWP (swap) instruction was added, allowing the programmer to atomically read and write to memory in one instruction.
Computers Using the ARM3
The next major release in the Acorn line-up was the 1991 A5000, a more business-oriented personal computer with a similar specification to the A540. It featured two MEMC1a chips, allowing for up to 8MB of RAM, an IDE interface, and a slot on the motherboard for the forthcoming FPA floating point unit. This was a spin-off of the technically similar RISC OS laptop project, the A4 -- so named because its footprint had the same dimensions of a piece of A4 paper.
The A5000 was revised in 1993 to an upclocked 18 MIPS 33MHz ARM3, at the same time as the release of a new series of low-end models, the A3010, A3020, and A4000. These new Acorn machines were no longer denoted "Archimedes", and were an attempt to gain wider market share. All three used fundamentally the same hardware: they were powered by the ARM250 processor, a system on a chip built around a 12MHz ARM2as core, which was effectively a cacheless, static ARM3. The ARM250 also included the MEMC1a, VIDC, and IOC support chips, all on one die, and produced aroud 7 MIPS on average. More importantly, it was manufactured for half the cost and used less than one third of the power of the chipset it replaced.
The ARM250 was the final Acorn RISC Machine produced before the processor business was spun off to become ARM Ltd. ARM's next architecture change, for the ARM6, was a larger step than the previous two. The ARM4 and ARM5 processors were never designed or manufactured: in the changeover from Acorn to ARM Ltd, the numbering scheme was changed to be more logical, and four and five were passed over.
- Used in: A540, R260, R225, A5000, A4
- Clock: 24MHz (A4), 25Mhz (A5000), 26Mhz (A540, R260, R225) and 33MHz (enhanced A5000, Simtec ARM3 upgrades)
- Fabrication: 1.5µm
- Registers: 16 general purpose, selectively banked
- Pipeline: three-stage
- Cache: 4KB data and instruction
- Addressing: 26-bit
- Architecture: ARMv2a
- Notable features: vast performance gains versus ARM2
- Based on: ARM2as core, MEMC1a, VIDC1a, IOC1
- Used in: A3010, A3020, A4000
- Clock: 12MHz
- Cache: none
- Architecture: ARMv2a
- Notable features: low cost, low power design with high performance/power ratio
"The ARM RISC Chip", Atack/van Someren, Addison-Wesley, 1993
"ARM System Architecture", Furber, Addison-Wesley, 2000
"ARM Chips List", Banks