instruction set, like most of the early 8-bit microprocessors, was quirky
. They all tended to have lots of special purpose instructions, like TSX
, rather than the more generalized MOV
like more modern processors. While the mnemonic
s are more a matter of style, the inconsistancies carried through to other aspects. The 6502 has a myriad of addressing mode
s, but which ones are available is highly dependant on which operations and registers are being used.
For example, here is a list of the addressing modes. Only the accumulator version of the instruction will support all modes; the rest support just the most important. The modes are:
- immediate: argument is value
- zero page: argument is 8-bit pointer to value within first 256 bytes of memory
- zero page, x: argument is 8-bit pointer, which is added to register x to get the value within first 256 bytes of memory
- absolute: argument is 16-bit pointer to value
- absolute, x: argument is 16-bit pointer, which is added to register x to get the value
- absolute, y: argument is 16-bit pointer, which is added to register y to get the value
- (indirect, x): argument is 8-bit pointer, which is added to register x to get another 16-bit pointer to the actual value
- (indirect), y: argument is 8-bit pointer to another 16-bit pointer, which is added to register y to the actual value
Here is a summary of the 6502 instructions:
AND (bitwise and memory with accumulator)
BIT (test bits between and memory and accumulator)
Only affects the flags. The Z flag is set if a bitwise and results in zero. V and S are loaded with bits 6 and 7 of the memory operand.
EOR (bitwise exclusive or memory with accumulator)
ORA (bitwise inclusive or memory with accumulator)
Shifts and rotates
ASL (arithmetic shift left)
The least significant bit becomes zero, and the high bit is shifted into the carry flag. This can be used for a unsigned multiply by a power of two.
LSR (logical shift right)
The most significant bit becomes zero, and the low bit is shifted into the carry flag. This can be used for a unsigned divide by a power of two.
ROL (rotate left through carry flag)
The carry flag is shifted into the least significant bit, and the high bit is shifted into the carry flag.
ROR (rotate right through carry flag)
The carry flag is shifted into the most significant bit, and the low bit is shifted into the carry flag.
ADC (add memory to accumulator with carry)
If the decimal flag is set, packed BCD addition is performed (i.e. 0x09 + 0x01 -> 0x10). If the flag isn't set, regular binary addition is performed. The 6502 has no add without carry instruction.
SBC (subtract with carry)
If the decimal flag is set, packed BCD subtraction is performed (i.e. 0x10 - 0x01 -> 0x09). If the flag isn't set, regular binary subtraction is performed. The 6502 has no subtract without carry instruction.
Increments and decrements
DEC (decrement memory)
DEX (decrement register x)
DEY (decrement register y)
INC (increment memory)
INX (increment register x)
INY (increment register y)
CMP (compare memory and accumulator)
CPX (compare memory and register x)
CPY (compare memory and register y)
TAX (transfer accumulator to register x)
TAY (transfer accumulator to register y)
TSX (transfer stack pointer to register x)
TXA (transfer register x to accumulator)
TXS (transfer register x to stack pointer)
TYA (transfer register y to accumulator)
Loads and stores
LDA (load accumulator)
LDX (load register x)
LDY (load register y)
STA (store accumulator)
STX (store register x)
STY (store register y)
PHA (push accumulator)
PLA (pull accumulator)
PHP (push processor status (flags))
PLP (pull processor status (flags))
Branches, jumps, and returns
Bcc (branch on condition code)
Branch on one of the S, V, C, or Z flags. The mnemonics are
BMI (plus or minus),
BVS (overflow clear or set),
BCS (carry clear or set), and
BEQ (not equal or equal), respectively. Only a one byte signed displacement can be used; for father branches the
JMP instruction must be used.
Always jumps to an absolute 16-bit address, either immediate or indirect. Buggy if the indirect address is on a page boundary.
JSR (jump to subroutine)
Pushes the program counter and jumps.
RTS (return from subroutine)
Flags sets and clears
Sflag (clear or set a flag)
The mnemonics are
SEC (clear and set carry),
SEI (clear and set interrupt),
CLV (clear overflow), and
SED (clear and set decimal). There is no instruction to set overflow.
Triggers an interrupt and skips a byte. This instruction pushs the program counter and the status register and does an indirect jump to an interrupt handler. Although the opcode is one byte, the instruction is treated as if it is two bytes long.
RTI (return from interrupt)
Restores the flags and program counter from the stack after an interrupt.