write-only memory

write-only memory n.

The obvious antonym to `read-only memory'. Out of frustration with the long and seemingly useless chain of approvals required of component specifications, during which no actual checking seemed to occur, an engineer at Signetics once created a specification for a write-only memory and included it with a bunch of other specifications to be approved. This inclusion came to the attention of Signetics management only when regular customers started calling and asking for pricing information. Signetics published a corrected edition of the data book and requested the return of the `erroneous' ones. Later, in 1972, Signetics bought a double-page spread in "Electronics" magazine's April issue and used the spec as an April Fools' Day joke. Instead of the more conventional characteristic curves, the 25120 "fully encoded, 9046 x N, Random Access, write-only-memory" data sheet included diagrams of "bit capacity vs. Temp.", "Iff vs. Vff", "Number of pins remaining vs. number of socket insertions", and "AQL vs. selling price". The 25120 required a 6.3 VAC VFF supply, a +10V VCC, and VDD of 0V, +/- 2%.

--The Jargon File version 4.3.1, ed. ESR, autonoded by rescdsk.

Write Only Memory does actually exist in the context of Handel-C, a programming language with a C-like syntax targetted at generating FPGA configurations.

Handel-C uses Multi-Port RAM structures (MPRAMs) to connect two independent code blocks. This is one method of creating a "port" between two processes.

When an MPRAM is declared the programmer can specify the level of access for each process. If a process needs to read and write to the port it is declared as "ram"; if it just needs to read from the port it is declared as "rom", and if it just needs to write to the port it is declared as "wom", or Write Only Memory. Using one-way rather than two-way structures simplifies the logic, and so takes up less valuable space on the FPGA.

For example, a structure which can be used to pass arrays of 8 bit integers from one process to another:

      mpram Port
      {
           rom <unsigned 8> Read[16];
           wom <unsigned 8> Write[16];
      }

When this code becomes part of an FPGA configuration, "Write" will be connected to the logic of the producing process, and "Read" will be connected to the logic of the consuming process. Any data stored in the structure by the producing process is, from the perspective of that process, gone forever; it cannot be read back.